Component pitch violates voltage clearances

[DanR]

Hi all,

A software engineer asked me a question the other day and I realised that I wasn't sure how to answer it.

He is working on a hobby project and has used an SMPS with a 60V output capability. I don't think he's actually using it at 60V, but it came up that this components pitch of 0.5mm violates the IPC standard for voltage clearance and creepage. If the pitch is 0.5mm then the clearance between pins, in air, is far less, and the same applies for the creepage between pads.

I've seen this loads of times but have never really stopped to understand why it's supposedly ok to break clearance rules within the components 'fanout' room. Can someone please help me?

P.S. I don't have a datasheet or schematics. Let's use this as a hypothetical to discuss layout.


Kind regards,
Dan

[robertferanec]

Knowing the part number would help

[qdrives]

With a 0.5mm pitch, make the pads 0.25mm and that leaves the spacing to 0.25mm too.
Apply conformal coating over this component to comply to IPC and IEC 60664 standards.
During layout, it is best to use a room (Altium) where the clearance rules a set to 'allow' this.

[DanR]

Knowing the part number would help

Thanks Robert,
He's using MAX15062. (package drawing, footprint drawing).
However, I've also seen this clearance issue with SOIC style packages that have pins violating clearance rules for a greater distance in air before they contact the PCB pads. And even then, the pads would be too close together.
I'd like to avoid focusing too much on that specific part if that's ok though. I think this question applies to a lot of parts.

With a 0.5mm pitch, make the pads 0.25mm and that leaves the spacing to 0.25mm too.
Apply conformal coating over this component to comply to IPC and IEC 60664 standards.
During layout, it is best to use a room (Altium) where the clearance rules a set to 'allow' this.

Thanks qdrives.
I appreciate the help but I'm trying to ask why it's ok to allow a different clearance within the component room. I am aware of how to do it.



Kind regards,
Dan

[DanR]

Maybe this extra information will help with my question.

For that specific SMPS, it's possible to meet the IPC-2221B requirements for minimum conductor spacing when it comes to the tracks, polygons, and planes that stem from the SMPS's pads. These sections of copper can be coated in soldermask, or can be located on an internal layer which drastically reduces the minimum spacing.
This is assuming that I'm correct in assuming that soldermask counts as a "permanent polymer coating". An assumption I'm not confident in.

However, the exposed pads are not coated in mask and they do violate the IPC-2221B minimum clearance.
The SMPS pins also violate the IPC-2221B minimum clearance. This is more noticeable in SOIC style packages than the component I linked in my previous reply.


Kind regards,
Dan

[qdrives]

A SOIC has 0.65mm pitch, while this TDFN has 0.5mm, so I do not know how it should be more noticeable for a SOIC? Because you see the pins?
"...why it's ok to allow a different clearance within the component room" - because this allows you to apply correct rules for the entire board, except for the room. And as I mentioned, you need to apply conformal coating to that section or pot the product to comply (IPC table A5 - https://external-content.duckduckgo....png&f=1&nofb=1 ).
It is almost impossible to apply conformal coating over the entire board.
And yes, soldermask is a permanent polymer coating.