Why is the propagation delay and pin package length zero for these DRAM pins?

[gyuunyuu1989]

Length matching is an important factor in the PCB design of high speed routes. The length actually starts from the output buffer on the die on one end and the input buffer on die in the other end. It needs to take into consideration the bounding wires inside the IC package, the IC pins that attach to the PCB, the PCB pads and the PCB tracks which also includes PCB vias and PCB pads.

From what I know, for Altium designer to correctly do the length matching, we also need to give the propagation delay inside the IC package to it. This can be entered into the part when we are doing the schematic symbol design of it.

When I look at the board design of Fedvel Academy "iMX6 Rex V1I1 Project Files saved in AD2014" it seems that the "propagation delay" and "pin delay length" are zero which means they have not been set. Why is this so? How can Altium designer do the length matching correctly in this case?

I believe only Robert can answer this question.

[robertferanec]

That feature did not exist in the old Altium. If there was a delay in package, the length was re-calculated in spreadsheets.

[gyuunyuu1989]

Isn't a delay in package always going to be there? Do I understand correct that you use a spreadsheet to make the calculation and then, assign that value to each net in the schematic manually? Maybe you have a video covering the idea behind my question.

[robertferanec]

Some chips have length matching done on the chip - in that case length in package is not required. About the spreadsheet, this can help: https://youtu.be/v1EzSt3TfZA