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  • Bermell
    replied
    Thank you very much Robert

    Leave a comment:


  • robertferanec
    replied
    Bermell it is possible to do via in pad ( as qdrives mentioned ). It has some advantages, as Steve.Picotest already mentioned, it is better way to connect decoupling capacitors and also sometimes it's done this way if there is no extra space for additional pads. However, it is more expensive, that is why it's not on many boards.

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  • Bermell
    replied
    Thank you very much for your answers

    Leave a comment:


  • qdrives
    replied
    As long as the via's are either:
    - Filled and capped
    - Solid copper fill

    Leave a comment:


  • Steve.Picotest
    replied
    See my EDICON paper on partial inductance this minimizes the mount portion if the inductance, making the capacitor much more effective at high frequencies (DDR, FPGA, etc)

    Leave a comment:


  • Bermell
    started a topic Decoupling capacitors placement

    Decoupling capacitors placement

    Hello Robert,

    Firstly, thanks a lot for your excellent work all these years.

    My question is about a strange placement of decoupling capacitors that i have seen in the following video:
    https://www.youtube.com/watch?v=R2fw2g6WFbg

    This video is a teardown of a Tektronix oscilloscope.

    Click image for larger version

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    In the capture attached, If you look at the decoupling capacitors, they are located exactly above the vias. And this happens for the memory chips (DDR4) and FPGA (Xilinx Ultrascale)

    What is your opinion about it? Is it possible to do this placement of the decoupling capacitors?

    Thank you very much in advance
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