Stackup for DDR3 memory chips

[Bermell]

Hello,

I would like to ask you about the following Stackup that I am going to use for the routing of 2 DDR3 memory chips and a FPGA

1.- Components
2.- GND
3.- Data bytes group
4.- Address command and control
5.- Power 1.5V
6.- Power 1.5V
7.- Address command and control
8.- Data bytes group
9.- GND
10.-DDR3 Clock, and components

I know, the most important groups, are the Data bytes. I mean, each data byte should be in the same layer and doing the same changes between layers, but what about address command and control group? I can't keep all the signals of this group in the same layer, so and this is my question, what do you think about using the layers 4 and 7 of my Stackup, for routing this group ?

Thank you very much in advance

[robertferanec]

It could be possible. Be super careful about parallel tracks on layers 3/4 and also on 7/8. If you are not sure, try to simulate it when you finish layout. However, personally I would probably add GND layers between 3/4 and 7/8 if that would be possible.

PS: From my experience usually it is not so simple to have 5/6 1.5V only, usually there are many other powers under the CPU/FPGA, so often these power planes can't be so simply routed over all the memory tracks.

[Bermell]

Thank you very much Robert. I am agree, it is always much better to use a GND plane as reference for the memory tracks

[Bermell]

Hello,

In addition to this present post, I did other one with the title, "About 1080 Prepreg for getting 40 Ohms Impedance in Top and Bottom layers"
in which I was thinking of using a Stackup similar to the one the OpenRex card has.

I am now considering using this new layers configuration:

1.- Components
2.- GND
3.- Data bytes group
4.- GND
5.- Power 1.5V
6.- Address command and control
7.- GND
8.- Data bytes group
9.- GND
10.-DDR3 Clock, and Address command and control

Layer 4, is not a GND power plane , but a GND polygon with the same size that the 1.5V polygon of layer 5

Can you give me your opinion about this new Stackup. What do you think about using the layers 6 and 10 of my Stackup, for routing Address command and control group ?
I know that the speed signals, will be different in layers 6 and 10.


Thank you very much in advance

[robertferanec]

I would try it.

PS: But I am still a little bit worried about not maybe not having enough space for power planes under your chip. Be sure you can connect all the powers before routing.

[Bermell]

Thank you very much for your answer, Robert.

Finally I have chosen to use 12 layers as you suggested in a previous comment, adding 2 GND layers to my Stackup

[binayak]

Bernell,

Just a doubt - are you using DIMM or individual chips? Only in the DIMM case, the CAC lines are referenced to power.