FEDEVEL
Platform forum

Bermell , 09-01-2022, 12:31 AM

Hello,

I am routing the layout using two DDR3 memory chips.

In my stackup, layers 3 and 10 have the same geometry and properties. The same happens with layers 5 and 8.
I am using the fly-by topology. For point to multi-point signals ( such as address command control and clock ), I've split these signals into two planes because I can't route them all on the same layer.

So for these signals, i use the 5 and 8 layers until the first memory chip, and 3 and 10 layers, between the first and second memory chips
My question is about vias and lenght matching.

How can I do lenght matching in my case ? Must I consider lenght vias used in the lenght matching ? Vias have different properties than layers ( different speed of signals )

I hope you can understand my question.

Thanks a lot in advance

robertferanec , 09-10-2022, 01:51 AM

Hmm, I have never done it this way - I keep the signals what belong together on the same layer and I do not split them into two layers. I do not like to depend on VIA properties as it is hard to be sure what they are and if the stackup has to be updated (e.g. you have to move PCB manufacturing to a different manufacturer), then all the calculations may not be accurate. If you can't fit them all on the same layer, you still can maybe split them between address, command and control if that helps.

Bermell , 09-10-2022, 07:34 AM

Thanks a lot for your answer.

But what do you mean when you talk about splitting address, command and control ?

robertferanec , 09-10-2022, 09:46 AM

sometimes there may be slight difference between these address command control groups in required length matching, but signals within group should have same/similar timing. so sometimes you can put some of these groups on different layers. Maybe have a look at SODIMM module examples, you can download schematic and pcb files from JEDEC website - have a look how they routed them.