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  • Trace Width/Gap

    In your course "Advanced PCB Layout" lesson 4 at 1:40 of the video you say that we should start with 0.1mm and then reduce it to 0.075mm at the end. This gives us a S/H=1.25 which is good but still not 5H or 7H as recommended in your table.

    My question is: It may be "better" but how do I know if it sufficient? You go to the trouble of creating this table and clearly stating S/H=5 and then you say that 1.25 is OK. Which is it? If it is 5 then I should start with a gap that will lead to this, no?? What did you do?

    10x for your great work.

    BTW: Can you tell me what drawing tool you used to draw the manual diagrams in the video?

  • #2
    APLC Lesson 4 at 1;40?

    Ideally you would like to have the gaps from table - these are safe numbers. However it may not be always possible e.g. because there is simply no space on your PCB for wider spaces. In that case you just make the space between tracks as wide as you can, you route them carefully in the groups (e.g. you can use smaller space between tracks with the same timing e.g. the same data bank) and if you don't feel confident, you need to simulate.

    I had to design number of PCBs where it was impossible to keep the distances from the table - usually because the board size had to follow a standard (e.g. PC104) or it had to be as small as possible. So in this cases, it's impossible to adapt board size to meet the numbers from the table and you have no other option than just use smaller spaces.

    I usually use the software delivered with my pen tablet - in that case it was https://www.artrage.com/ but now I use https://www.clipstudio.net/en/

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    • #3
      Hi Robert,

      Thanks for your reply.

      Do you simulate? If not, then how do YOU know that it is good enough? Obviously the rule and table are there to define what is safe.

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      • #4
        In most cases I do not simulate. If I simulate, it is only because I broke recommended design rules by a lot (e.g. often design guide will tell you what space / gap they recommend and you can calculate crosstalk coefficient from it - use Saturn PCB Toolkit - and compare the coefficient with your design) and if it is an important interface e.g. memory layout.

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        • #5
          So your table is effectively not practical because it is not generally feasible to implement such gaps. Hence, the only way to design is to use a design guide, if it exists. Otherwise, it's just luck or simulation. So what's the point of the table exactly?

          BR

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