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Time delay and impedance for Vias

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  • Time delay and impedance for Vias

    ​If you use xsignals , how do you use vias?
    Altium shows 0 ps for time delay in vías.

    About via impedance, i think Robert has said before, It is only important for very high speed, not for example for DDR3

    How do you think what is the best way, for knowing time delay in vias?
    Besides, this time is very different in vias or single tracks​. The antipad is important too
    I have split addr cmd control group in 2 layers with the same propagation delay, so i need to know time delay for vias

    And a last question, what antipad do you recommend for vias in DDR3 ?

    ​​​​​​Thank you very much in advance​

  • #2
    when routing you should always have the same layer changes for each group. either datallines address lines. this way you do not have to think about it.
    so try and re route it. if youb can't then you have some room in your control / addr lines since they operate at half the speed.
    also try and fix in some gnd via's next to your layer transistions

    not sure if x-signals takes via length into account but still.. better to be on the safe side and keep layer changes to the same per group.

    with regards to via impedance. if you can then do it. why not.. it just setting up proper clearances between also setup gnd via's parrallel next to the diff pairs if you can.

    antipad for you via is basically your impedance control for a via, but its dependend on your layerstack./material . ,use saturn pcb and calculate it

    good luck


    • #3
      simplest is just to add the extra distance in the via to the other tracks on different layers, but I do not know how to calculate it exactly. however if you are not sure, it should be possible to simulate it. If you are still not sure, you can have a look at reference designs of memory modules. I think some of them have address bus routed on different layers, you can check the length and what they did.

      PS: I agree with Paul van Avesaath. I have had to separate address group in some designs, but if it's possible I try to avoid it.