Layer stackup, USB hub, vias routing

[MLc]

Hello, I am working on my Master (university) project(100W PD, USB 3.0 hub). I would need advice on a few things to make my design as good as possible.
1. My board is 4L (1L=signals+power, 2L=GND plane, 3L=signals, 4L=signals+power). I route all USB traces on TOP and L2 is reference GND plane. I read that it is better not to pour gnd polygon near that usb interface/traces due to impedance. What about bottom layer? Can I pour GND under usb hub driver and the usb traces?

2. I have maybe bad setup or rule for vias but some vias whose going from 1L to 4L or to 2L but not are connected in 3L so in 3L I see their pad. Leave it as it is or remove the unused vias pads from 3L? (For example the pads on picture)


3. When I combine in stackup mid layers - plane and signal I got warning "impedance deviation found". Some advice? Is this a problem? But differential routing worked.


My last question.. In USB-C connector layout I needed to connect their pads. It looks messy My question is that according to my stackup which layer would you recommend me to use for those links? 3L or 4L?


Thank you MLc.

[qdrives]

1a) You can pour Gnd on the bottom without problems.
1b) On the top you may want to keep a higher clearance against the high speed signals. Does pouring Gnd it make it better? One thing is important -- keep the amount of copper balanced compared to the stack symmetry, otherwise you get 'banana' boards.
1c) Make sure that the traces below the USB connector will not short to the connector shell.

2) Either you through hole via's or blind, burries or microvia's. There is back drilling for TH via's if they are used in high speed. Most fabricators want you to leave unused pads, but allow them to remove them.

3) Say you specified 50 ohm traces but set the width to become 35 ohm. Than fall outside the tolerance, hence the deviation. More importantly, if you supplied a bigger picture we could see...


4) If you put the high speed on L4, do add some Gnd vias too, especially close to A11/A10. L3 and L1 (top) both reference the same return layer.

[MLc]

Hi,
Thank you for answer.
1b) What do you mean with "banana board"? Can you explain it? I don't know this term.
2) I forgot to say... all the vias are through hole.
3) I have 90ohm diff impedance set.

4) one more question ... pour GND polygon on TOP under DC-DC inductors?

Thank MLc

[qdrives]

1b) The technical term is bow and twist, with assembly warpage. In my case the with one end flat on a table would raise the other end (300mm) 1cm high.
2) I guessed that, but still then you either do back drilling or leave the unused pads and let the fabricator remove them. There is the option in Altium with the export (gerber, ODB+) to remove the unused pads (include unconnected mid-layer pads). Option is missing in Gerber X2 and IPC2581.
3) Better pictures, Could it be that traces already on the board do not conform to the rule/impedance?
4) Just two posts out of many:

https://www.signalintegrityjournal.com/blogs/17-practical-emc/post/2694-dc-dc-converters-solid-return-plane-or-cutouts-under-switch-node-and-inductor

https://media.monolithicpower.com/mps_cms_document/m/p/mps_emc_optimized_buck_converter_layout_28.04.2020.pdf

[MLc]

Hi, thank you for information.
Also I fix the warning "impedance deviation found". I change L2 setup - "plane" to "signal" and pour GND in that layer.

[qdrives]

I change L2 setup - "plane" to "signal" and pour GND in that layer.

I do not know why that would "fix" the problem. Perhaps it was the non-symmetrical layout...

[Paul van Avesaath]

might be me but your via's do seem a bit off meaning the annular ring seems a bit small? what sizes are you using

[MLc]

I am using 0.3/0.6mm default, but some vias have smaller ring -> 0.5/0.3mm

[Paul van Avesaath]

ok that is ok..
also add some gnd via's near your ssrx and ssrtx diffpair via's because you are transisitoning your higspeed usb lanes there needs to be a proper gnd via next to them