Length maching, RF & signal track impedance calculation
Andrius , 04-27-2016, 12:54 AM
Hello, I have 3 questions, maybe other will find them interesting too 
:
1) Imagine you are length matching signals CAS and RAS for DDR2/DDR3. Is it OK to match just the total length of RAS and CAS, or do I need to match length on separate layers?
For example do I need to have a2=b2 ? (please see attached length matching photo)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2) Robert in course lessons spoke about updating default track width (0.1mm) to 50ohm impedance.
a) When using very thin prepreg (it is good because it reduces crosstalk between signals) track width for 50ohms can get as small as 0.075mm (2.95mils) i'm a bit afraid to use tracks smaller than 0.1mm..Because of added cost, and maybe it can break during production.
The question is: Is is easy for most Asian PCB manufacturers to make for example 0.075mm tracks (i order boards only in Asia because of smaller cost)? Maybe we should always design stackup so that we to get bigger (0.1mm) tracks that has 50ohm impedance?
b) I often use this 6 layer stackup (please see attached stackup photo). I have these transmission line structures on top layer:
-0.3..0.5mm width RF tracks (wider tracks has less loss)
- 0.1mm signal tracks (DDR2). I use smaller tracks to save PCB space.
Both structures requires 50 ohm, but it's impossible to meet this if both traces signal layer is L1 and reference layer is L2. How to get 50ohm for both traces?
I have come up with a two options:
- Make prepreg between L1 and L2 smaller: about 0.1mm, so that signal tracks would have 50ohm impedance.
For the RF tracks, cut polygon under RF tracks on layer L2. Make L3 as a reference plane for RF tracks (only add GND polygon under tracks, other PCB area is left for signal tracks.)
(please see attached modified stackup photo)
- Ignore that the signal tracks on Layer1 has significantly higher than 50ohm impedance.Make signals short on layer L1,try to put most signal length on L3 and L4.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
3) About Diff pairs impedance calculation. I have diff pairs on layer L3. The reference planes are L2 and L5 (one reference plane is very close and other is far – about 1mm, there are also tracks on L4 that crosses diff pair).
Am I calculating diff pair impedance the right way? Do you do the same?
When I calculate impedance with Saturn PCB, it gives me warning because one of the planes if far from signal layer (but I believe the plane that is far does not contribute much to the impedance value)
(please see attached original 6 layer stackup photo )
Thanks
:1) Imagine you are length matching signals CAS and RAS for DDR2/DDR3. Is it OK to match just the total length of RAS and CAS, or do I need to match length on separate layers?
For example do I need to have a2=b2 ? (please see attached length matching photo)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2) Robert in course lessons spoke about updating default track width (0.1mm) to 50ohm impedance.
a) When using very thin prepreg (it is good because it reduces crosstalk between signals) track width for 50ohms can get as small as 0.075mm (2.95mils) i'm a bit afraid to use tracks smaller than 0.1mm..Because of added cost, and maybe it can break during production.
The question is: Is is easy for most Asian PCB manufacturers to make for example 0.075mm tracks (i order boards only in Asia because of smaller cost)? Maybe we should always design stackup so that we to get bigger (0.1mm) tracks that has 50ohm impedance?
b) I often use this 6 layer stackup (please see attached stackup photo). I have these transmission line structures on top layer:
-0.3..0.5mm width RF tracks (wider tracks has less loss)
- 0.1mm signal tracks (DDR2). I use smaller tracks to save PCB space.
Both structures requires 50 ohm, but it's impossible to meet this if both traces signal layer is L1 and reference layer is L2. How to get 50ohm for both traces?
I have come up with a two options:
- Make prepreg between L1 and L2 smaller: about 0.1mm, so that signal tracks would have 50ohm impedance.
For the RF tracks, cut polygon under RF tracks on layer L2. Make L3 as a reference plane for RF tracks (only add GND polygon under tracks, other PCB area is left for signal tracks.)
(please see attached modified stackup photo)
- Ignore that the signal tracks on Layer1 has significantly higher than 50ohm impedance.Make signals short on layer L1,try to put most signal length on L3 and L4.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
3) About Diff pairs impedance calculation. I have diff pairs on layer L3. The reference planes are L2 and L5 (one reference plane is very close and other is far – about 1mm, there are also tracks on L4 that crosses diff pair).
Am I calculating diff pair impedance the right way? Do you do the same?
When I calculate impedance with Saturn PCB, it gives me warning because one of the planes if far from signal layer (but I believe the plane that is far does not contribute much to the impedance value)
(please see attached original 6 layer stackup photo )
Thanks
robertferanec , 04-27-2016, 01:30 AM
1) For memories I do not normally length match on individual layers.
Note: don't forget, you are not length matching the total length, you are length matching the segments withing net and pin-to-pin copper distance. Some information can be found for example in iMX6 Design Guide (from page 38)
2)
a) We have designed, manufactured and sold a lot of boards with tracks below 0.1mm, no problems. We do also designs with bigger tracks e.g. download OpenRex (we use 0.114 - 0.120 mm / 50 OHMs there) or have a look at my post: Download PCB Stackups – Free for your Projects
b) Interesting. I never had to do anything like this. Maybe I would think about using "For the RF tracks, cut polygon under RF tracks on layer L2". Think about return currents.
3) That is how I would calculated too. I do sometimes see Saturn complains, but usually I am able to design the stackup the way that the error is not there. Even if you calculate 2 layer PCB (where the thickness is 1.6mm) you still should be able to get good numbers with no errors. Maybe the tracks are too thin?
Note: don't forget, you are not length matching the total length, you are length matching the segments withing net and pin-to-pin copper distance. Some information can be found for example in iMX6 Design Guide (from page 38)
2)
a) We have designed, manufactured and sold a lot of boards with tracks below 0.1mm, no problems. We do also designs with bigger tracks e.g. download OpenRex (we use 0.114 - 0.120 mm / 50 OHMs there) or have a look at my post: Download PCB Stackups – Free for your Projects
b) Interesting. I never had to do anything like this. Maybe I would think about using "For the RF tracks, cut polygon under RF tracks on layer L2". Think about return currents.
3) That is how I would calculated too. I do sometimes see Saturn complains, but usually I am able to design the stackup the way that the error is not there. Even if you calculate 2 layer PCB (where the thickness is 1.6mm) you still should be able to get good numbers with no errors. Maybe the tracks are too thin?
Use our interactive Discord forum to reply or ask new questions.