Hi Robert,
In lesson 3 of the Fedevel Advanced PCB Layout Course you showed us how to calculate the crosstalk using the Saturn PCB toolkit for a reset line that was placed in close proximity of a clock signal. I'm now wondering what happens if a differential signal pair doesn't have enough clearance between each trace. If for example the positive differential pair signal has 3.3V for a logic high and the coupled voltage is 2.9V, and the negative differential pair signal has a -3.3V for a logic high and the coupled voltage is -2.9V does this mean that I will see 0.4V (3.3V-2.9V) at the positive differential pair signal and -0.4V (-3.3V+2.9V) at the negative differential pair signal?. Would this possibly prevent a logic high from being set as the difference between the pair is now 0.8V and not 6.6V?
In lesson 3 of the Fedevel Advanced PCB Layout Course you showed us how to calculate the crosstalk using the Saturn PCB toolkit for a reset line that was placed in close proximity of a clock signal. I'm now wondering what happens if a differential signal pair doesn't have enough clearance between each trace. If for example the positive differential pair signal has 3.3V for a logic high and the coupled voltage is 2.9V, and the negative differential pair signal has a -3.3V for a logic high and the coupled voltage is -2.9V does this mean that I will see 0.4V (3.3V-2.9V) at the positive differential pair signal and -0.4V (-3.3V+2.9V) at the negative differential pair signal?. Would this possibly prevent a logic high from being set as the difference between the pair is now 0.8V and not 6.6V?
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