Announcement

Collapse
No announcement yet.

Single DDR3 routing

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • robertferanec
    commented on 's reply
    E.g. Freescale / NXP has something: Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces http://www.nxp.com/files/32bit/doc/a...n&fileExt=.pdf

  • robertferanec
    commented on 's reply
    In fly-by you can do this between group length matching in the first segment of signal (the place between CPU and first memory chip) e.g. make the first segment of CLK a little bit longer than ADDR/CMD/CTL group, then CLK will always arrive a little bit later then ADDR/CMD/CTL.

  • JohnsonMiller
    replied
    In DDR2/DDR3 T-branch routing there are two sets of constraint: 1) inside group (ex. data lines), 2) between groups. For example clock signal need to have some relation with DQS. Question is that in Fly-by routing of DDR3 it is not possible to follow this rule! Am I missing or misunderstanding something?

    Leave a comment:


  • JohnsonMiller
    replied
    From board design point of view, what is major difference between DDR3 and DDR4? Can you recommend a tutorial of help document?

    Leave a comment:


  • robertferanec
    replied
    mairomaster is right. Everything is correct except the typo in 4). Tolerance should be followed according to the chip manufacturer (sometimes the numbers are different). Normally we use:

    - "within 5 mils" between P/N of differential pair,
    - "within 10 mils" for Data group (we keep DQS longest from the group)
    - "within 20mils" for ADDR/CMD/CTL group.

    Have a look at this iMX6 Design guide and if you do not have any other documents, you could possibly use it as a reference (page 40): http://cache.freescale.com/files/32b...6DQ6SDLHDG.pdf

    Click image for larger version

Name:	ddr3 length matching rules.jpg
Views:	284
Size:	117.2 KB
ID:	2985

    Leave a comment:


  • mairomaster
    replied
    I think you got it right, just for 4) it is cock pair, not clock enable pair but I guess that is just a typo.

    The tolerance should be specified by the manufacturer of the FPGA you are using. Standard values that I am using are something like withing 0.5 mm (+/- 0.25 mm) for the signals withing a group and 0.2 mm withing a differential pair (+/- 0.1 mm between the positive and negative signal in the pair).

    Leave a comment:


  • key2
    started a topic Single DDR3 routing

    Single DDR3 routing

    I am doing an opensource FPGA + DDR3 design, I was watching your great tutorial about routing with altium and particularely the tutorials about DDR3 routing, but one thing that is not clear:

    When you have a SoC or FPGA connected to a single DDR3, what are the groups ?

    If I got it well:

    1) data0-7 + dqs0_pair + LDM
    2) data8-15 + dqs1_pair + UDM
    3) ADDR0-x + BA0-2 + RAS/CAS/ODT/CKE/WE
    4) DDR CKE_pair

    Am I correct or could it be split more than that ?

    What is the tolerence that is acceptable ?

    regards

Working...
X