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Decoupling capacitors layout

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  • Decoupling capacitors layout

    Hi everyone,

    When I route decoupling capacitors on my PCB's(usually 4 layer boards with MCU) i place them as close as possible to the VCC/GND pins and place vias to reference planes. One wouls probably use this strategy when doing layout for CPU boards also. By using this strategy all of transient HF currents are flowing through reference planes, in my case GND and VCC plane.

    I noticed however this may not be a good approach since I no longer have reference plane but center fed patch antenna. See what Olin(a guy with the highest rating on electronics.stackexchange says about that).

    "The solution I usually use, and for which I have quantitative proof it works well, is to keep the local high frequency currents off the ground plane. You want to make a local net of the microcontroller power and ground connections, bypass them locally, then have only one connection to each net to the main system power and ground nets. The high frequency currents generated by the microcontroller go out the power pins, thru the bypass caps, and back into the ground pins. There can be lots of nasty high frequency current running around that loop, but if that loop has only a single connection to the board power and ground nets, then those currents will largely stay off them."

    It may be harder to do the layout but it makes perfectly sense to do it that way. However, I've seen many professional designs and neither one is using this kind of approach. Here's what Olin says later on

    "Here's a anecdote that shows how this stuff can make a real difference. A company was making little gizmos that cost them $120 to produce. I was hired to update the design and get production cost below $100 if possible. The previous engineer didn't really understand RF emissions and grounding. He had a microprocessor that was emitting lots of RF crap. His solution to pass FCC testing was to enclose the whole mess in a can. He made a 6 layer board with the bottom layer ground, then had a custom piece of sheet metal soldered over the nasty section at production time. He thought that just by enclosing everything in metal that it wouldn't radiate. That's wrong, but somewhat of a aside I'm not going to get into now. The can did reduce emissions so that they just squeaked by FCC testing with 1/2 dB to spare (that's not a lot). My design used only 4 layers, a single board-wide ground plane, no power planes, but local ground planes for a few of the choice ICs with single point connections for these local ground planes and the local power nets as I described. To make a long story shorter, this beat the FCC limit by 15 dB (that's a lot). A side advantage was that this device was also in part a radio receiver, and the much quieter circuitry fed less noise into the radio and effectively doubled its range (that's a lot too). The final production cost was $87. The other engineer never worked for that company again."
    We could all agree that 15dB on FCC is a lot!! He claims also that for many number of cases, power planes are unnecessary if decoupling is properly done.

    What are your thoughts guys?

  • #2
    I always filter powers. Normally, there is one big power rail and I create number of local power nets, each use BEAD/Ferrite/0R + decoupling capacitors. I like this solution - not only because of better filtering, but I like to have option to measure currents or, if I need, disconnect the local powers (good for debugging). For processor boards (which I normally design), I do not split GND. From my measurements, splitting GND was worse for EMI and ESD, than using a solid GND plane for the whole board - again, I am speaking about CPU boards, for different kind of boards you may need a different approach.

    BTW: I have never seen a CPU design splitting GND planes under CPU - nor AMD Reference designs, nor Intel motherboard designs.

    Check out iMX6 Rex Module Schematic, how the power rails are done - for example see the page 13 (Ethernet):

    Click image for larger version

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    • #3
      Thank you Robert!

      I think that approach may be interesting in the MCU board design. There is an actual reference plane for the fast signals, while HF currents of the decoupling capacitors will stay off the reference plane causing less interference.

      I did not also seen using this approach in any CPU board design.


      • #4
        It came to my mind somehow. What's the point of having a total PWR plane dedicated to one voltage level(i.e. 3V3) and use ferrite beads to filter component voltages(i.e. 3V3_ETH_AVDDH)? The signal return path won't flow on that plane anyhow because of large impedance between local component voltage level and big power plane.


        • #5
          tuv0k I was not really investigating deeply how effective it is and I have not done any power simulations and analysis comparing a connection with and without a bead. I would say, the local decoupling and bulk capacitors may play some role in return path.