DDR2 Placement and Routing

[robertferanec]

[email protected] I am not really sure what would you like to hear I can not say if its good or bad - if I was doing it, I would use 10 layer stackup ... for example, from my experience one PWR plane is not enough.

[[email protected]]

Thanks Robert for your kind suggestion,
now i have changed the above stackup as per below, kindly check is this ok.

Layer Number	Layer Name	Material Type
1	Top	Dielectric
		Conductive
2	GND1	Dielectric
		Conductive
3	Inner 1(DDR Signals)	Dielectric
		Conductive
4	Inner2(DDR Signals)	Dielectric
		Conductive
5	PWR	Dielectric
		Conductive
6	Inner 3(DDR Signals)	Dielectric
		Conductive
7	GND2	Dielectric
		Conductive
8	Bottom(DDR Signals)	Dielectric
		Conductive

Regards,
Venkatesh N

[robertferanec]

Hi [email protected] it really depends on your circuit and design. You will need to be aware of your DDR2 track routing, reference planes, possible crosstalk between L3/L4 and currents flowing through the GND plane.

I normally don't use 8 layer PCB, because I always prefer to have at least one solid neighbour GND plane per high speed signal layer.

[[email protected]]

Hi Robert,
I am using following 8 layer stackup, in this my doubt is i am using only one GND can you check is this ok r not,

Layer Number	Layer Name	Material Type
1	Top	Dielectric
		Conductive
2	GND	Dielectric
		Conductive
3	Inner 1	Dielectric
		Conductive
4	Inner2	Dielectric
		Conductive
5	PWR1	Dielectric
		Conductive
6	Inner 4	Dielectric
		Conductive
7	PWR2	Dielectric
		Conductive
8	Bottom	Dielectric
		Conductive

Regards,
Venkatesh N

[robertferanec]

Maybe we would try to do it this way - see the attached picture. However, I am not saying that this is the way you should do it nor that it is the best way to do it. It is just an initial idea.

[robertferanec]

[email protected] please, I try to help, but I do not review designs. Thank you very much for understanding.

[[email protected]]

Thank you very much Robert for your great time and kind support,
OK i will do length matching as per the byte group method and i will send you the final PCB file for your kind review and feedback.



Regards,
Venkatesh N

[robertferanec]

How many signal and power/gnd layers do you have? Where exactly data / add / cmd / clk signals are placed on the CPU?

[robertferanec]

I don't know exactly what could be the best placement - you will need to play with it and think about how the layers will be used. The goal is to have same length between the VIA (where ADD/CMD/CTL signals splits) and each memory chip + have option to place termination resistors very close to the VIA. We will try to draw an image to explained it better.

[[email protected]]

ECC chip is placed on bottom side

[[email protected]]

you mean that to place ECC chip in between two other devices.


Regards,
Venkatesh N

[robertferanec]

The middle of the ECC chip rotation should be in the center of the ECC chip.

[[email protected]]

If i rotate ECC chip by 180 deg it will overlap on processor, find the attached placement file for your reference.


Regards,
Venkatesh N

[robertferanec]

This is how I would probably do that:

1) I would probably rotate the ECC memory chip by 180 Deg. I would also consider to place all the termination resistors in the place where the ADD/CMD/CTL splits (use minimum stubs). I would try to make all the three branches same length (from split to each memory chip). And, I would simulate it to see if the signals are ok.

[[email protected]]

Then how you will propose placement in this case and can you please let me know how to route VTT.


Regards,
Venkatesh N