Double DDR3 Routing

[PeterZ]

Dear Forum,
i try to route two DDR Chips in Fly-by but i can´t route all Adress an Control lines in one layer (L3). In the OpenRex Board some lines route in layer 3 and some in layer 8, but mixed up not from 0 to 7 and 8 to 15. I thought its important to route all Adr/Control Signals on the same layer? I have a 6 layer Board.
Another question is, why should i place the decoupling caps on the Top (same side as DDR chip) if i can place the caps closer to the vias on the Bottom?
Thank you

[robertferanec]

Hi Peter,
- Routing the group by same topology (on same layers) is a really good rule for everyone, it always works ok. However, there are situations when you may want to break it. Once you feel confident in doing memory layouts, you can do it the same way as on OpenRex (they do it the same way also on some memory modules), this helps with fly-by topology and it will work perfectly.

- If you have place on the bottom, yes, you can place the decoupling capacitors there.

[PeterZ]

Dear Forum,
i have place my DDR3 Modules and route the adress and control signals (length match still missing). But is it better to route it on the same layer(brown) or is it better to route the signals from the layer 4(blue) furthermore on layer 4(blue). If i route the signals from layer 4 to the processor in layer 4 the way is shorter and the via count is fewer.

[robertferanec]

I would definitely keep the same number of VIAs in the group.

[znp2015]

Dear PeterZ,
If you have two DDR3, why don't you put the one DDR3 on top and another one on the bottom? I think in this way you can do the fanout of DDR3 very nice and use T-branch to do the layout. It was described perfectly at the advance course of FEDEVEL academy by Mr. Robert.

Let's try.

Best Regards,
Mostafa

[znp2015]

Dear PeterZ,
You should take the advanced course from fedevel academy site.

Best,
Mostafa

[znp2015]

I commented that there is an exception that you can use T-branch for DDR3 (thanks to Mr. Robert in lesson 6, advance course) when you are using imx6 and i think that your cpu is also imx6!!!

[PeterZ]

Dear znp2015, i have only 2 DDR3 ICs. I think T-Branch is better for 4 ICs. The Processor is a AM3358 Sitara not a IMX6. I found no lesson 6 on youtube.
Dear Robert, if i keep the same number of vias i route some lines "completely" in L3 and some in L4. This way is more easily but is this ok? In your IMX6 design you go on the same layer to route the Addr/ctrl lines to the processor. If i route it on L3 and L4 it has the same ground reference in the middle and the same count of vias, i think that is a good choice.
Thanks PZ

[robertferanec]

if i keep the same number of vias i route some lines "completely" in L3 and some in L4. This way is more easily but is this ok?

I am not really sure what do you mean - keeping same number of VIAs, but routing it differently. Would you just place a VIA on track and the VIA would go basically nowhere?

[Arash yahyapour]

Hi dear Robert Thank you for your helping in your mail.
I have a question about length matched on DDR2.
In my design I used a lot of square wave track.and the speed is 2.5 ns. I worrying for inductive noise.
my design is different with your design, you did to length match manually. but I used auto length matched.
Brown track is differential CLK.
do you announce your opinion please?
thank you
Arash

[robertferanec]

Arash yahyapour have a look at this post and watch the video - it may help: High Speed PCB Design Rules (Lesson 4 of Advanced PCB Layout)

Three things what I noticed:
- I would make the space between "waves" bigger
- I would not use 90Deg angles (even some people say it's not a big deal)
- I am not really sure what is topology of the layout ... e.g. do you use T-Branch balanced topology for Add/Cmd/Ctl signals? Have a look at some of my older videos: Altium Designer – DDR2 routing and layout video

[Arash yahyapour]

Hi dear, first , thank you for your replay
Ok. I used T-Branch between two DDR2 chips and they are balanced exactly.
But these balance is different between two data line.
for example T-Branch balanced between two chips in D0 line and it is 461 mil. but T-Branch balanced between two chips in D1 lineand it is 870 mil. however, both of total length is matched with less than 10 mil different's.
I think there is no problem in here because Z-in from my processor to the two chips is the same.
please, kindly if I'm wrong, notify to me.
thank you Mr.Robert
Arash

[robertferanec]

Ok ... so both chips are connected to the same data bus? What is the frequency of the memory?

PS: Maybe it would help if in the picture you highlight the groups individually (e.g. Bank0 data group, addr/cmd/ctl group, etc.)

[Arash yahyapour]

Hi Dear Robert
yes, both of chips are connected to the same data bus. and the frequency is 400 MHz, 2.5 ns
please let me, I doing to modify my design compatible with your opinion
Ok after that I will share it for you
the best regards
Arash

[robertferanec]

By same data bus, you mean for example, D0 is connected to both chips? If yes, hmm, once you done the layout, maybe try to simulate it. Balanced T-Branch still could work ok for 400MHz Data signals, but it may depend on termination.

If I need to place memory chips on the same bus, I place them on top of each other (one on TOP and one on BOTTOM side of PCB), so the branch on data signals is as short as possible. This keeps quality of the signal high.

[Arash yahyapour]

Hi My friend thank you for your attention.
yes it is correct. But it will be difficult to installation of chips.in this method (one on TOP and one on BOTTOM side of PCB) we need oven box for installation. and I can not use hot air.
so, I do it, I designed for two week just terminal between my processor and two DDR2 and Know I will remove all of them.
Because I know your experience is higher than me.
thank you
have a nice time
Arash

[Arash yahyapour]

Hi Mr. Robert.
could you more explain about this sentences :"If yes, hmm, once you done the layout" and "but it may depend on termination",
I have two pins named CS. by these pins I will activate one chip and deactivate another chip and send 16 bit data to one chip,
in this case I need complete of data on one chip because it will doing for image processing and it will be easy for processing programming.
I you have any opinion for this (my hardware) please kindly to send me.
the best regards
Arash

[robertferanec]

... I have two pins named CS. by these pins I will activate one chip and deactivate another chip and send 16 bit data to one chip, ...

This is exactly what the problem could be. You only talk to one of the memory chip at the speed of 400MHz and there is a part of track (connected to the non-active chip) "hanging" around which can cause reflections and which can influence quality of the signal (make it worse). That is why I place chips on top of each other, so the part of the track which is "hanging around" is as short as possible.

PS: We were discussing similar situation (but FLASH + SDRAM on same data bus) with much slower speed here - you can see how splitting the data signal can influenece the signal quality: http://www.fedevel.com/designhelp/fo...ecommendations

[Arash yahyapour]

Hi my friend how are you?
I changed my design accordance with your recommendation. and I send screenshot of Address and data and command, Separately,
I don't length match yet,
could you see thier, and send me your recommendation please.??
I want use midlayer1 (under top) for ground and differential clock only. is it ok ?
thank you
the best regard
Arash

[robertferanec]

Which tracks are data and which are address? Also, for data, you can do bit swapping to make the layout even better (to be able to place VIA directly close to pad) - you can safely swap bits within byte (e.g. you can swap bits D0-D7), do not swap bits between bytes. Have a look at some DDR2 recommendations: Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces

[Arash yahyapour]

From left: 1-All. 2-Address. 3-Data for DDR_1 . 4-Data for DDR_2 . 5- Commands