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LPC1788 with SDRAM and FLASH layout.

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  • robertferanec
    replied
    I have never used LPC1788, but I guess they may for example need additional memories to process and store some data.

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  • yasin.bahrami
    commented on 's reply
    What are the advantages of boosting NANDflash external and SDRAM external in LPC 1788?

  • robertferanec
    replied
    Please, could you clarify your question? I am not really sure what you mean.

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  • yasin.bahrami
    commented on 's reply
    Thanks for answering my question in the comment below

  • yasin.bahrami
    replied
    Hello
    Someone can tell me what applications NandFlash and SDRAM are in connection to LPC 1788

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  • robertferanec
    replied
    that's what I would do
    PS: Posielam pozdrav do Ciech

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  • MartinHonig
    commented on 's reply
    Thank you for your feedback Robert.

    I was thinking about resistor arrays in series with signals (slowing the edges if necessary), or proposed 0R to remove stubs if there is just BGA assembled.

    I will try to do a quick mock up and check if the routing is going to be still "nice enough". Stubs are hidden in internal layer covered with ground plane, but I assume that VIAs can do the magic and as you mentioned, you never know.

  • robertferanec
    replied
    MartinHonig, I would simulate it.

    15-40MHz doesn't look much, so the interface may just work, but you are right, even after simulation, it will not be clear how this may influence EMI. The important factor will be rising/failing speed of the signals.

    I guess, board may work perfectly and pass EMC/EMI even with the stubs, but .. there is this but ... and what if ...

    Maybe, what could also be a solution (maybe what I would do), is place 0R resistors on the bottom under the BGA. it looks like there may be some space for them. If you find out, that you do not need the 0R resistors there (e.g. you run EMC/EMI tests with BGA and 0R fitted), then just remove them in next revision.


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  • MartinHonig
    replied
    Hello Robert,

    I have noticed, that znp2015 used a combined footprint for SRAM (BGA or SOP) for a RAM. I am facing similar dilemma.

    I would like to create an "universal" PCB for SLC NAND Flash memory (8-bit paralel bus + control signals connected to Cortex-A processor) for TSSOP48 and BGA63 packages. My concern is that when there is going to be the BGA package used, it is going to have roughly 8mm stubs because of unused traces to TSSOP footprint. I checked the NAND driver header for frequency settings across various vendors and we are talking about 15-40MHz, just to set a ballpark regarding how much high-speed we are talking about.

    Is it an issue, or this 8mm long stubs should bearable in this application?

    I also have concerns in term of erradiated EMI.

    Click image for larger version

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  • robertferanec
    replied
    You are designing SDRAM which works differently comparing to DDR3, so requirements for routing are different. SDRAM / NAND is more like a standard parallel bus. So you need to be careful about crosstalk / reflections and strobe signals coming at the right time (not before the data). Length matching between LPC and SDRAM and length matching between LPC and NAND would not be so critical (I would just probably try to make the strobe signals a little bit longer then data signals). But because you are placing two different chips on one bus, more critical will be the way how you route the tracks and the way how you place the chips on the bus (because of possible stubs when you are communicating with one of the chips). The most important is probably to keep the bus short. If you are not sure if you placed the components correctly and if you would like to check reflection for different scenarios of communication , you can try to simulate it. We were speaking about something similar here: http://www.fedevel.com/designhelp/fo...ecommendations

    I hope this helps.

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  • znp2015
    replied
    I did some length matching for control, address, clock, and data signals. I do not really know that it is okay or not. Please give me a comment on this length matching.

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  • znp2015
    replied
    I am really glad to find someone that can answer my obvious questions :

    1) the address, control, and data bus (32 bit) pins are really spread in the LPC1788 BGA package. This really makes the design hard. Because as I saw in the DDR3 layout, everything was designed wisely and engineer have good options to layout each buses locally. By the way, I have seen the embedded artist board and it works really nice. So I decided to continue choosing the LPC1788 in BGA format. I have this questions that how the line matching is important in this situation? Can I do the layout just considering the same topology for the important bus? In some application notes, it is mentioned that it just need to keep the same bus in the given area, for example less than 6 inches. I have this question, when the distributions of important buses are really spread, it means that the line matching is not important with high margin (as I learning from Robert, the line matching is for arriving the signal at the same time)?

    2) The frequency of LPC1788 is 120 MHz and the RAM is less than 100 MHz. How is about the cross talk and the high speed design mentioned in the FEDEVEL ACADAMY. Does it consider as high speed frequency circuit?

    thank you so much.

    Best Regards,
    Mostafa

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  • znp2015
    replied
    The existing board has an external bus and they are buffered. In this regards, i also buffer only the pins used in the flash!

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  • robertferanec
    replied
    Do they use the buffer in the reference design? If you are not sure, follow schematic and layout of an existing and reliably running board - I would do that.

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  • znp2015
    replied
    excuse me for the mistake in the picture. i wrote SDRAM instead of SDCARD. left down side of picture.

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