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Via length consideration for length matching DDR3/LPDDR/DDR3

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  • Via length consideration for length matching DDR3/LPDDR/DDR3

    I am doing single rank ddr3 routing in a 6 layer board with the following stackup:-
    Signal(L1) -> Gnd(L2) -> Signal(L3) -> Pwr(L4) -> Gnd(L5) -> Sig(L6)
    Click image for larger version

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    (I am using Saturn PCB Toolkit for calculations)
    Add Table
    Via(L1-L6) Via(L1-L3)
    Height 38 mils 12 mils
    Step Response 15.8 ps 4.1 ps

    Signal Propagation Speed
    Top/Bottom 145 ps/in
    Inner Layer 175 ps/in

    I am confused which parameter to consider for length matching. Physical length or the Timing.

    Lets say i have a 1.4 in trace in inner layer(L3) with two vias of length 12 mils each from Top layer to L3.
    Total Length = Trace Length + 2 * Via Length
    (I am not including Fan out Stub here)
    Flight Time = length * propagation delay => 1.4*175 = 245ps
    Length (inch) Via (mils) Via mils Total
    L3(DQ)
    Length (in) 1.4 0.01 0.01 1.42
    Flight Time (ps) 245 4.1 4.1 253.2
    L1-6(Addr/Cmd/Control) 0
    Length (in) 1.36 0.04 0.04 1.44
    Flight Time (ps) 197.2 15.8 15.8 228.8
    L1(clk)
    Length (in) 1.45 0 0 1.45
    Flight Time (ps) 210.25 0 0 210.25
    Note: on top layer there is only clock differential pair without any Via. That's why i made it 10 mils longer to compensate. Also signal travels much faster in diff pair.

    So in all the above cases the difference in Physical Length is 30 mils while the timing difference is 40ps. If i try to match according to the length then i have a bigger flight time difference and vice versa.

    I would like to know that with the above calculations am i going in the right direction for ddr3 routing. I am curious to know which factor to take into account if going for much higher speed in GHz range. I know the tolerance depends on the timing budget. But excluding all these things which is the correct way for matching, Physical Trace Length or the Flight time.

    I am a newbie. So sry if i asked something stupid.

    thanks and regards

  • #2
    The signals worry about timing, not about length. The reason why length is commonly used for matching is because the software has an easy way to measure it. However, if you use the same layers for particular group of signals and you have the same length on all layers, you will optimally achieve the same timing.

    Comment


    • #3
      himanshusharma0192 to explain it very simply, e.g. to make memory works correctly, some signals have to arrive at the same time to the chip (or almost at the same time). To achieve this, you need to know how fast signal is travelling and what is the distance it needs to travel. The thing is, that speed of travelling can be different between layers. If you route some signals inside PCB and the other signals outside of PCB, they will not arrive at the same time (even if the length is same, they will not arrive at the same time, because some signals will travel faster than other signals). That is, why sometimes you can see the numbers in time delay.

      However, not every software can calculate the travel time of a signal accurately. Also designing PCB based on time delay may not be sometimes a good idea (e.g. you change PCB materials or stackup and your PCB may stop work). So, there are some techniques, which allow you to use track length matching instead. This can be done if you follow some conditions - for example, when you route the signals the same way / topology. This means, if you route the signals (which you would like to match) through the same layers and through same number of VIAs, then when you length match them, the signal will arrive at the same time. If the signals are extremely sensitive, you may need to keep same / similar length between the signals on every layer.

      PS: I never really on designing PCB based on delay (to make some signals longer / shorter to compensate the delay) as we had once problems with this. I prefer to use same topology routing and do length matching.

      Comment


      • #4
        Thanks for the explanation robertferanec and mairomaster. Thanks a lot.

        Comment


        • #5
          Thank robertferanec .Big answer.I always worry about this problem.And its clear after read your comment,

          Comment


          • #6
            Originally posted by robertferanec View Post
            himanshusharma0192 to explain it very simply, e.g. to make memory works correctly, some signals have to arrive at the same time to the chip (or almost at the same time). To achieve this, you need to know how fast signal is travelling and what is the distance it needs to travel. The thing is, that speed of travelling can be different between layers. If you route some signals inside PCB and the other signals outside of PCB, they will not arrive at the same time (even if the length is same, they will not arrive at the same time, because some signals will travel faster than other signals). That is, why sometimes you can see the numbers in time delay.

            However, not every software can calculate the travel time of a signal accurately. Also designing PCB based on time delay may not be sometimes a good idea (e.g. you change PCB materials or stackup and your PCB may stop work). So, there are some techniques, which allow you to use track length matching instead. This can be done if you follow some conditions - for example, when you route the signals the same way / topology. This means, if you route the signals (which you would like to match) through the same layers and through same number of VIAs, then when you length match them, the signal will arrive at the same time. If the signals are extremely sensitive, you may need to keep same / similar length between the signals on every layer.

            PS: I never really on designing PCB based on delay (to make some signals longer / shorter to compensate the delay) as we had once problems with this. I prefer to use same topology routing and do length matching.
            ​For DDR3 layout we must use one on top layer, other on bottom layer. Via length about 48 mil (for example). We still haven't final conclusion on this, have you simulate or experiment with this? must calculate via length?

            Comment


            • #7
              Yes agree with above viewers, Same layer and same via count are important for signals to reach the end point at same time.

              Comment


              • #8
                Originally posted by mohsin_qau View Post
                Yes agree with above viewers, Same layer and same via count are important for signals to reach the end point at same time.
                ​More difficult one is not the same layer? what is precision determination?

                Comment


                • #9
                  ​For DDR3 layout we must use one on top layer, other on bottom layer. Via length about 48 mil (for example). We still haven't final conclusion on this, have you simulate or experiment with this? must calculate via length?
                  I am not exactly sure about your connection. If you need to have two memories on top of each other, there are two situations:

                  - Top and Bottom memories are connected to the same memory signals (e.g D0-D7, D8-D15). Here you need to use through hole VIAs and pin swapping (so pads with same data signal are on the top of each other). The difference in the last segment VIA between Top and Bottom layer is not critical as data byte will always be length matched correctly (the group of data always goes to one particular memory chip together with its strobe signals). Only what will be difference is slight mismatch between last segment length on the branches.

                  - Top and Bottom memories are connected to different data signals (D0-D7, D8-D15, D16-D23, D24-D31). Here you need to use uVIAs

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                  • #10
                    Thanks Robert, I well understood the reason for using through hole.

                    Comment


                    • #11
                      I have done the clam shell with ddr3 and through hole via's.. could be better with uVia's but works without.. it's a bit more work though. but I had it simulated and got no real timing issues.
                      make sure you get the "T" structure between the top and bottom chips the same. and like said before above keep all datagroups dm and dqs on the same layer.

                      good luck

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                      • #12
                        Do you mean two DDR3 chips on top of each other connected to the same data bus? Yes, that should work oki with through hole VIAs. Important is, that data pads needs to be on top of each other (so the last segment is as short as possible).

                        Comment


                        • #13
                          As my study, when designing DDR operating at clock higher than 1GHz, we should concern about type of micro vias/ buried via. If < 1GHz through hole via still work fine.

                          Comment


                          • #14
                            I know this post is old but I'd like to check something.
                            For the flight time in the table above, the step response of the via is used for the flight time in the via. But is that correct? Isn't the step time of the via just a measure of its bandwidth?
                            Shoudn't we use something else for the via time ? Like the propagation velocity in the dielectric ?

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                            • #15
                              if you keep via transition and via count the same it should not matter right? it should all be equal so it cancels itself out in calculations.

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