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Via length consideration for length matching DDR3/LPDDR/DDR3

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  • #16
    Originally posted by himanshusharma0192 View Post
    I am doing single rank ddr3 routing in a 6 layer board with the following stackup:-
    Signal(L1) -> Gnd(L2) -> Signal(L3) -> Pwr(L4) -> Gnd(L5) -> Sig(L6)
    [ATTACH=CONFIG]n4176[/ATTACH]
    (I am using Saturn PCB Toolkit for calculations)
    Add Table
    Via(L1-L6) Via(L1-L3)
    Height 38 mils 12 mils
    Step Response 15.8 ps 4.1 ps
    Signal Propagation Speed
    Top/Bottom 145 ps/in
    Inner Layer 175 ps/in

    I am confused which parameter to consider for length matching. Physical length or the Timing.

    Lets say i have a 1.4 in trace in inner layer(L3) with two vias of length 12 mils each from Top layer to L3.
    Total Length = Trace Length + 2 * Via Length
    (I am not including Fan out Stub here)
    Flight Time = length * propagation delay => 1.4*175 = 245ps
    Length (inch) Via (mils) Via mils Total
    L3(DQ)
    Length (in) 1.4 0.01 0.01 1.42
    Flight Time (ps) 245 4.1 4.1 253.2
    L1-6(Addr/Cmd/Control) 0
    Length (in) 1.36 0.04 0.04 1.44
    Flight Time (ps) 197.2 15.8 15.8 228.8
    L1(clk)
    Length (in) 1.45 0 0 1.45
    Flight Time (ps) 210.25 0 0 210.25
    Note: on top layer there is only clock differential pair without any Via. That's why i made it 10 mils longer to compensate. Also signal travels much faster in diff pair.

    So in all the above cases the difference in Physical Length is 30 mils while the timing difference is 40ps. If i try to match according to the length which is usually done in the
    pcb industry then i can have a bigger flight time difference and vice versa.

    I would like to know that with the above calculations am i going in the right direction for ddr3 routing. I am curious to know which factor to take into account if going for much higher speed in GHz range. I know the tolerance depends on the timing budget. But excluding all these things which is the correct way for matching, Physical Trace Length or the Flight time.

    I am a newbie. So sry if i asked something stupid.

    thanks and regards
    I know I am replying to an old thread but I really wanted to know the answer and found one so i'll try replying even though I don't know if this will be helpful
    So you want the signals to arrive at the same time right? So the only way to go would be by matching the timings and not the length. But if the signals are on the same layer then you will have to match the length as the propagation speed will have to be same for all. I think for this you will need an advanced software system for high speed. This is the only insight I can give! Thanks
    Last edited by Stephbaker; 12-11-2018, 10:21 PM.

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    • #17
      Hi steph, you are right. but in most cases you have to post-simulate the layout to really fine tune it. Altium is pretty powerfull it can manage it.. but you have to know what you are doing. and simulating is not possible in altium so you will always need a 3rd party program like hyperlynx to run the simulation.

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