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Strategy to route a Giga Ethernet Phy and RJ45

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  • Strategy to route a Giga Ethernet Phy and RJ45

    Hi everyone,

    I would like someone to help me choose the best strategy to route this gigabit PHY ethernet.

    The problem is that the differential pairs MDI0 (MDI0_p & MDI0_N), MDI1, MDI2 and MDI3 are opposed to the rj-45 connector, I would like to place all the important components on the top: Click image for larger version

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    I'm thinking about changing the RJ-45 connector, the problem is the RJ-45 of Wurth Elektronik 7499111614A, is designed for Low EMI, and I would like to use it:

    Any suggestion?

    Best regards.
    Last edited by oscargomezf; 09-28-2016, 02:50 AM.

  • #2
    I've found a solution, but I have to route in two layers per differential pair. I'd rather use only one layer, but it's impossible or I'm not able to find the solution:

    Click image for larger version

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    I'm nor sure if the routed differential length is enough precise:

    ETH2_MDI0_N -> 32.254 mm
    ETH2_MDI0_P -> 33.671 mm
    ETH2_MDI1_N -> 33.957 mm
    ETH2_MDI1_P -> 33.855 mm
    ETH2_MDI2_N -> 33.698 mm
    ETH2_MDI2_P -> 32.241 mm
    ETH2_MDI3_N -> 32.756 mm
    ETH2_MDI3_P -> 32.889 mm

    What do you think about my design?

    I forgot to say that D7 and D6 are ESD diodes. And the stack-up is:

    L1 (Signal-RED) - L2 (GND) - L3 (Signal-Light Blue) - L4 (GND) - L5 (PWR) - L6 (PWR) - L7 (GND) - L8 (Signal-light brown) - L9 (GND) - L10 (Signal-Blue)

    Best regards.


    • #3
      I love chip manufacturers who consider layout to create great pinout How do they do it in reference design?


      • #4
        Hi Robert,

        Do you think it could be a good design strategy? I would have liked to route everything in the same layer without vias but it was impossible.

        Now I'm concerned about the length matching of the differential pair.
        Do you think it could be good enough?

        Click image for larger version

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        Best regards.


        • #5
          oscargomezf, how they do it in reference design? Do you have a screenshot from their layout (the chip manufacturer reference board)?


          • oscargomezf
            oscargomezf commented
            Editing a comment
            I'm sorry, but I don't have any reference design. I'm waiting for Marvell. But It's a typical gigabit ethernet.

            Best regards.

        • #6
          Are you entirely sure you are connecting the signals the right way? I've used very similar PHYs and normally you don't need to cross the tracks like that. Can you provide a closer screen shot with the nets of each track visible?


          • #7
            Hi Mario,

            I attached you two screen shots. I think the problem is the gigabit ethernet IC. This is the pinout:

            24 -> MDIP0
            23 -> MDIN0
            22 -> POWER
            21 -> POWER
            20 -> MDIP1
            19 -> MDIN1
            18 -> MDIP2
            17 -> MDIN2
            16 -> POWER
            15 -> POWER
            14 -> MDIP3
            13 -> MDIN3

            I was reading different datasheets of 1000 Ethernet Transceivers, for example, LAN8820, LAN8810 and KSZ9021RL. They have this type of configuration that is easy to route:

            XX -> MDIP3
            XX -> MDIN3
            XX -> -
            XX -> -
            XX -> MDIP2
            XX -> MDIN2
            XX -> MDIP1
            XX -> MDIN1
            XX -> -
            XX -> -
            XX -> MDIP0
            XX -> MDIN0

            The solution could try to find an RJ-45 (with integrated magnetics) with another type of pinout but I think there isn't anyone.

            However, although you can see the track crossover, If you see the stackup, they are between GND Planes:

            L1 (Signal-RED) - L2 (GND) - L3 (Signal-Light Blue) - L4 (GND) - L5 (PWR) - L6 (PWR) - L7 (GND) - L8 (Signal-light brown) - L9 (GND) - L10 (Signal-Blue)

            So they are electrically separated, Do you still think it's not a good idea to route the PCB in this way?

            Best regards.
            Attached Files


            • #8
              Maybe, they designed the chip to be on the other side of the board That is why I am so curious about their reference design - to see how they placed the chip vs. connector and how they connected them together in PCB.

              PS: Even your implementation may work just fine. I have designed couple of boards where PHY signals went through board to board connectors and were routed on several different layers - but the truth is, I always try to route all the signals on the same layers. In your case you route each pair on different layers.


              • oscargomezf
                oscargomezf commented
                Editing a comment
                Ok, thank you very much, Robert.

                I'm going to try to get a reference design, but Marvell is very fussy with their documentation. I had to sign an NDA for a simple datasheet.

                Best regards.