Hi Dear Robert.
I Want To Design 2 DDR3 Ram With ZYNQ FPGA. I Watch Your Video And Other. I Have Some Question.
1: I don't Know How to Draw The Layout And What Should I Consider From Impedance,Routing Track Length Matching And High Frequency PCB Design Consideration. From Where I Must Start Routing. Please Tell Me Some useful Resource About BGA And DDR3 Routing, High Frequency PCB Design Consideration.
2: In Impedance Calculation Formula, Why we don't Consider Track Length.
3: I want use 8 layer. what is the best stack-up?(How Many Signal And Plane Layer And Where they must be Located)
4: How Many Routing Topology Is there(fly-by , T and ...). I Want Some Resource To Learn About Them.
Thank's.
I Want To Design 2 DDR3 Ram With ZYNQ FPGA. I Watch Your Video And Other. I Have Some Question.
1: I don't Know How to Draw The Layout And What Should I Consider From Impedance,Routing Track Length Matching And High Frequency PCB Design Consideration. From Where I Must Start Routing. Please Tell Me Some useful Resource About BGA And DDR3 Routing, High Frequency PCB Design Consideration.
2: In Impedance Calculation Formula, Why we don't Consider Track Length.
3: I want use 8 layer. what is the best stack-up?(How Many Signal And Plane Layer And Where they must be Located)
4: How Many Routing Topology Is there(fly-by , T and ...). I Want Some Resource To Learn About Them.
Thank's.
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