Power Plane

[robertferanec]

You may try to import the Altium files into KiCAD, but I am not sure if that will work oki.

I think Altium has a viewer, maybe that could help? However, I do not know what are the capabilities of the viewer and what are the conditions to get one.

[MadhuWesly]

Hi Robert,
I have designed an HDI PCB, in that I have created multiple polygons in different layers for a single power net. For example, consider we have VDDSOC power net, for this I have created polygon on L1(Top layer), but the created polygon is not solid(it is like discontinuous islands) that is why I have again created polygon on L3 signal layer as well in order to make it strong plane.

Actually, I do not know if it is correct way or not. Will it create any problem?
Please let me know if there will be any serious problem with this approach in my board.

Thanks & regards,

[robertferanec]

I often make partial polygons on top/bottom layer and then more solid polygon also inside PCB. No problems.

PS: Also, for very high currents we draw exactly the same polygons on multiple layers.

[MadhuWesly]

Thanks for the reply Robert, thats a valuable information to me. Please let me get clarification on few more doubts:

1. In the following image the component is a PMIC which is generating supplies like 2A, 1.5A, 700mA, etc. I have drawn the traces in such a way that the trace width is small at the PMIC pins and increased trace width as it goes out. I also created polygons in different layers for the source.
a. Will it be able to carry the required current to the destination properly?
b. What is maximum acceptable length till that we can maintain small trace width and then make the trace wide?
c. please look into the components placement around the PMIC and give better suggestions.

2. Do we have to maintain good amount of spacing between control signals, enable signals and other signals like power traces, or any other noise signals?

awaiting your reply.

Thanks and regards,
Madhuwesly.

[mairomaster]

Prioritise placing the big output inductors as close to the PMIC as possible. You can put most of the small capacitors on the bottom layer, so that you have more space for the inductors at the top. That will allow you to use thicker tracks for the outputs.

Cross-talk should be less of an issue in the case - just try to be sensible.

[MadhuWesly]

Can you please reply inlines to the questions.

Thanks in advance.

[robertferanec]

MadhuWesly, you may want to have a look at our Switching Power Supply course: https://www.fedevel.com/academy/onli...design-course/

Possibly, you can download our OpenRex Altium project and check out how we did the placement and routing of PMIC: http://www.imx6rex.com/open-rex/

a) you need to check maximum current for tracks and VIAs. Simple and free tool to do that is Saturn PCB toolkit: http://www.saturnpcb.com/pcb_toolkit.htm
b) c) for high currents and important loops in power supply I often use polygons instead of tracks. Usually the placement needs to be done the way, that current loops between inductors, transistors and output bulk capacitors are as small as possible. The best is to read layout section of a power supply chip e.g. have a look at this document (search for "PC Board Layout Guidelines"): https://www.intersil.com/content/dam...6/isl6236a.pdf

2) Read the document from 1 b) c) that may help you. You may need to be careful about routing signals close to some of the power supply signals (e.g. gate or tracks which are going to be very noisy)

[MadhuWesly]

thank you Robert.