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  • #16
    One thing I could find weird is "maintaining Drill- 0.15mm, and Pad- 0.5", will it create any difficulty in terms spacing? Actually, I didn't find anything weird other than that.

    Please let me know if you find any issue if we go with the specifications.


    • #17
      Check out their note about minimum TW (track width) for inner layers, change the units to mils and compare it with what they are suggesting - especially L3 / L6 100OHMs


      • #18
        Hello Robert,

        Thank you for your previous response.
        I would like to get one more confirmation, please clarify this:

        SoC specifications: iMX6Q - MCIMX6Q5EYM10AC of pitch 0.8mm, and Ball pad diameter - 0.5mm.
        Manufacturer minimum specifications: Drill size - 0.15mm, Pad size - 0.5mm.

        Can I achieve 0.1mm minimum spacing between Ball pad to Via(0.5mm-pad, 0.15mm-Drill) when I place vias in the BGA?

        When I was going through your course you mentioned your design rules as: Min clearance: 0.15mm - sqpinternational, Drill size: 0.2, and diameter:0.45mm.
        How would it possible to you to maintain 0.15mm spacing after placing 0.45mm Via in the BGA?

        Awaiting your reply.


        • #19
          You can check our open source OpenRex project:

          You can download the Altium files and measure all the dimensions you need to know. I will help you to answer your questions.