DDR3 Data bus minimum trace length?

[AndersM]

Hi

I'm currently working with the layout of a board using 2 DDR3 memories and a FPGA.
The board has really limited board space so I have to place the memory chips very close to the FPGA IC. However the documentation for the FPGA memory controller specifies that the MINIMUM trace length of the data bus should be "nominal 1-5 inches". (Xilinx UG583, table 2-5, p31)

Why not 0-5 inches?
What would the consequences be if I routed with 0.75 inches instead?

My guess is that this is because they also specify that it's ok to use smaller trace widths in the breakout area of the FPGA and the memory chip, so for the impedance to be dominated by the long sections of the trace then they would have a certain minimum length depending on the fanout trace length...

But if that's the case then it should be fine to use shorter traces if I can fan out using the recommended trace widths.
Is this assumtion valid or are there any other aspects that I've overlooked?

Thanks.

[robertferanec]

Hello AndersM. I apologize for late replay. I am travelling and have limited access to internet.

I checked the table and that is only a nominal value. I would not worry about it. I would use shorter tracks.

[AndersM]

I agree with you, but I don't understand why for example 0.5 inches would be a less nominal trace length if shorter traces are better?

Are there any minimum propagation delays required on the data buses or something similar?

[robertferanec]

In some special cases, there may be minimum propagation delay required (may depend on memory controller capabilities). Yes, I agree, the table definitely can confuse people, so maybe if you are not 100% try to ask XILINX.

[AndersM]

Ok, thanks for the input, much appreciated!