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ddr3 flyby matching CKE and RESET address and control

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  • Mihai
    replied
    Indeed, that's what I was thinking, but I was looking to have also an answer from you, just to be sure.
    Thanks!

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  • robertferanec
    replied
    I believe, RESET is asynchronous and it doesn't need to be length matched. I believe, routing RESET on different layers should be fine - just be aware of neighbor signals and possible crosstalk.

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  • Mihai
    replied
    Hi robertferanec ,

    So, as I see here and also find in your public design the DDR reset signal is not length matched to the CTRL and ADDR group (also there are no rules in the design guides about it, at least I didnt see them). However, I see that you have routed it on a different layer with respect to the CTRL and ADDR group(e.g. OpenRex project). How critical is this signal in terms of length or timing? I am planning to routed it with high clearance and almost the same length but on a different layer (bottom instead of an inner layer), due to the lack of space.

    Thanks,
    Mihai

    Leave a comment:


  • Via
    replied
    I did not change anything on board!
    Is actually always Hi, I have another issue that shutdown command just reset the board!
    I'm not think so that has relation to CKE signal!
    Last edited by Via; 12-27-2017, 06:20 PM.

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  • robertferanec
    replied
    Did you put the CKE to pernament Low? Or what helped?

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  • Via
    replied
    Finally, the processor detected 1G memory and boot to Linux!
    That was so great! Without CKE length matching!
    Robert Thankkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk youuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu uuuuuuuuuuuuuuu!

    Leave a comment:


  • Via
    replied
    Thank you Robert for all your help and consideration!

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  • robertferanec
    replied
    I have not used A64. I am not sure what are the recommendations for length matching. Each chip is different and it is important to check documentation.

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  • Via
    replied
    Here is Length matching for Olimex-A64 !
    What do you think?

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  • Via
    replied
    Originally posted by robertferanec View Post
    Via, maybe a bug?
    I did not think so, xSignal detect all signal between two chips, I used a lot!

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  • Via
    replied
    I checked my reference design made by KiCAD software,The DDR3 chip that I used is just use CKE0
    I think maybe for DDR3 Chip that don't have CKE1 ( more than 1G memory size) maybe is not need to length matching CKE signal!

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  • robertferanec
    replied
    Why xSignal feature did not add CKE as DDR3 control signal!! ?
    Via, maybe a bug?

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  • Via
    commented on 's reply
    Why xSignal feature did not add CKE as DDR3 control signal!! ?

  • Via
    commented on 's reply
    When Altium xSignal choice the address and data signals there is not CKE on it! I draw my DDR3 fly-by tracks with xSignal but leaved CKE! without length maching with other control signal!
    I sent my board to manufacturer, it maybe doesn't work?

  • diegopm
    replied
    Ok, I have discover that it is possible to add manually new xsingnals. Altium xsignals wizard do not include CKE by default.

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