Polygon Pour Clearance

[Michael Karl]

Hello
I have a question about flooding planes between VIAs.
In the photo you can see a clearance from 0.07mm. This is for the PCB-manufacturer too small.
Even the DRC could not find this.
I did designs with FPGA and DDR3 where a lot of VIAs are and I have also a lot of this too small clearances between the VIAs.
Can I set somewhere a rule to ckeck this?
Otherwise I have to manually inspect all my planes.

Sorry for my poor english. I am from Austria.

Many thanks in advance
Mike

[robertferanec]

We always check this visually/manually. I am not sure if there is a rule for this.

[Michael Karl]

Thank you for this advice.

[robertferanec]

Maybe you can setup a rule - VIA to VIA and set minimum clearance between them to the value when you know the copper will flow uninterrupted between them. Just an idea.