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Polygon Pour Clearance

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  • robertferanec
    replied
    Maybe you can setup a rule - VIA to VIA and set minimum clearance between them to the value when you know the copper will flow uninterrupted between them. Just an idea.

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  • Michael Karl
    replied
    Thank you for this advice.

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  • robertferanec
    replied
    We always check this visually/manually. I am not sure if there is a rule for this.

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  • Michael Karl
    started a topic Polygon Pour Clearance

    Polygon Pour Clearance

    Hello
    I have a question about flooding planes between VIAs.
    In the photo you can see a clearance from 0.07mm. This is for the PCB-manufacturer too small.
    Even the DRC could not find this.
    I did designs with FPGA and DDR3 where a lot of VIAs are and I have also a lot of this too small clearances between the VIAs.
    Can I set somewhere a rule to ckeck this?
    Otherwise I have to manually inspect all my planes.

    Sorry for my poor english. I am from Austria.

    Many thanks in advance
    Mike
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