picosecond to Mil conversion.

[Paul van Avesaath]

Hi Guys,

I am working on an awsome project with a XCVUP13P and 16 DDR4 memories over 4 controllers.
but I am struggling with one part of it.

I get a min and max delay in picosecond from vivado, and I need to figure out how to compensate that into my layout with altium. but since I can give internal wirebond delay into altium but only in mil I have to re calaculate that.

I know the Tpd that I am working with ( in my case 0.163 ps/mil megtron 6G) so calculating the delay should be easy right..
Maybe I am over thinking this but here is what I am doing.

Vivado gives a pin file with all the delays in a min/max configuration.
So I take the average of those numbers. And convert them to mil. and then need to do some correction due to "." to "," conversion.

but to what is it referenced?
Since I am working with a 4x16 bits DDR4 controller I am referencing it per byte group of 16 bits.
Basically saying I am matching within 16 bits and the respective Data masks and strobe pairs..

Pin Number	Site	Site Type	Min Trace Delay (ps)	Max Trace Delay (ps)	AVG Trace Delay (ps)	Correction value (ps)	Trace Delay (Diff per bank) (ps)	Trace length compensation (Mil)	Trace length compensation (mm)	Signal Name	Signal ID
AJ27	IOB_X0Y156	IO_L1P_T0L_N0_DBC_63	107.354	108.433	107893,50	107,89	58,89	361,26	9,18	ddr4_a_dm_n[7]	DATA
AH34	IOB_X0Y169	IO_L7P_T1L_N0_QBC_AD13P_63	165.952	167.620	166786,00	166,79	0,00	0,00	0,00	ddr4_a_dm_n[6]	DATA
AH28	IOB_X0Y162	IO_L4P_T0U_N6_DBC_AD7P_63	110.451	111.561	111006,00	111,01	55,78	342,17	8,69	ddr4_a_dqs_t[7]	DATA
AH29	IOB_X0Y163	IO_L4N_T0U_N7_DBC_AD7N_63	110.499	111.610	111054,50	111,05	55,73	341,87	8,68	ddr4_a_dqs_c[7]	DATA
AH31	IOB_X0Y175	IO_L10P_T1U_N6_QBC_AD4P_63	139.173	140.571	139872,00	139,87	26,91	165,10	4,19	ddr4_a_dqs_t[6]	DATA
AH32	IOB_X0Y176	IO_L10N_T1U_N7_QBC_AD4N_63	139.343	140.743	140043,00	140,04	26,74	164,05	4,17	ddr4_a_dqs_c[6]	DATA
AK31	IOB_X0Y167	IO_L6N_T0U_N11_AD6N_63	133.437	134.778	134107,50	134,11	32,68	200,46	5,09	ddr4_a_dq[63]	DATA
AJ31	IOB_X0Y166	IO_L6P_T0U_N10_AD6P_63	130.151	131.459	130805,00	130,81	35,98	220,72	5,61	ddr4_a_dq[62]	DATA
AG30	IOB_X0Y165	IO_L5N_T0U_N9_AD14N_63	127.892	129.177	128534,50	128,53	38,25	234,64	5,96	ddr4_a_dq[61]	DATA
AG29	IOB_X0Y164	IO_L5P_T0U_N8_AD14P_63	126.953	128.229	127591,00	127,59	39,20	240,43	6,11	ddr4_a_dq[60]	DATA
AJ30	IOB_X0Y161	IO_L3N_T0L_N5_AD15N_63	120.500	121.711	121105,50	121,11	45,68	280,21	7,12	ddr4_a_dq[59]	DATA
AJ29	IOB_X0Y160	IO_L3P_T0L_N4_AD15P_63	119.778	120.982	120380,00	120,38	46,41	284,66	7,23	ddr4_a_dq[58]	DATA
AK28	IOB_X0Y159	IO_L2N_T0L_N3_63	106.290	107.359	106824,50	106,82	59,96	367,82	9,34	ddr4_a_dq[57]	DATA
AJ28	IOB_X0Y158	IO_L2P_T0L_N2_63	105.926	106.991	106458,50	106,46	60,33	370,06	9,40	ddr4_a_dq[56]	DATA
AF33	IOB_X0Y180	IO_L12N_T1U_N11_GC_63	143.001	144.438	143719,50	143,72	23,07	141,49	3,59	ddr4_a_dq[55]	DATA
AF32	IOB_X0Y179	IO_L12P_T1U_N10_GC_63	142.763	144.198	143480,50	143,48	23,31	142,96	3,63	ddr4_a_dq[54]	DATA
AG32	IOB_X0Y178	IO_L11N_T1U_N9_GC_63	141.359	142.780	142069,50	142,07	24,72	151,62	3,85	ddr4_a_dq[53]	DATA
AG31	IOB_X0Y177	IO_L11P_T1U_N8_GC_63	141.364	142.785	142074,50	142,07	24,71	151,59	3,85	ddr4_a_dq[52]	DATA
AG34	IOB_X0Y174	IO_L9N_T1L_N5_AD12N_63	159.278	160.879	160078,50	160,08	6,71	41,15	1,05	ddr4_a_dq[51]	DATA
AF34	IOB_X0Y173	IO_L9P_T1L_N4_AD12P_63	163.226	164.867	164046,50	164,05	2,74	16,80	0,43	ddr4_a_dq[50]	DATA
AJ33	IOB_X0Y172	IO_L8N_T1L_N3_AD5N_63	143.138	144.577	143857,50	143,86	22,93	140,65	3,57	ddr4_a_dq[49]	DATA
AH33	IOB_X0Y171	IO_L8P_T1L_N2_AD5P_63	144.555	146.007	145281,00	145,28	21,51	131,92	3,35	ddr4_a_dq[48]	DATA

I am basing the calculation on the longest line within that group. And calculating the lengths needed to compensate to that length. hence getting the max values and subtracting the value of the delay. so in the end 1 line does not have to be matched and all others will be matched according to that group.



Does this makes sense?

The numbers of compensation length feel so big to me, that’s why I also have put in the mm to get a feeling of length and it seems ok, but still very long almost 10mm and I have no reference to see if this correct..
Anyway the next step would be to put these numbers into the Altium and figure out if Xsignals can help me with machting

let me know if I am approaching this in the correct manner.

Many Thanks
Paul

[robertferanec]

What is "XCVUP13P", I can not find any info about it? If it's an FPGA, you should be able to run a calibration or something and you may be able to adjust the delay in your chip (firmware).

[Paul van Avesaath]

Hi Robert, sorry, there was a typo. Its the xilinx ultrascale plus xcvu13p..

Wat i am trying to do is to get a better understanding if the calculation is correct and if it is normal to compensate thise large numbers. 10mm looks very long to me..

Best regards
Paul

[robertferanec]

Double check how other do it.

I was working on a project based on Altera chip with 4 memory slots and we have done the length matching the standard way. I am not 100% sure, but I believe, they then had some calibration firmware which they run on the physical board, and get values which they used to adjust their own firmware.

It may be something similar with XILINX, this is what I found as an example (https://www.xilinx.com/support/docum...cale-mis.pdf):

"Physical Layer – The physical layer provides a high-speed interface to the SDRAM. This layer includes the hard blocks inside the FPGA and the soft blocks calibration logic necessary to ensure optimal timing of the hard blocks interfacing to the SDRAM. "

.. and then it continues ...
"Calibration – The calibration modules provide a complete method to set all delays in the hard blocks and soft IP to work with the memory interface. Each bit is individually trained and then combined in order to ensure optimal interface performance. Results of the calibration process will be available through the Xilinx debug tools. After completion of calibration, the PHY layer presents raw interface to the SDRAM."

[Paul van Avesaath]

Hi Robert,

,,Double check how other do it. ''

thats what I am trying to do here


the thing is, I tried to look at the defkits, and finaly managed to get some orcad files into altium. then the confusion started. it did not make sense!
i recalculated the matching they did on the VCU190 and it did not match. not in a good way. that lead me to contact xilinx themselves, and the answer was that you should not trust the matching on the defkits, since they are not likely to be 100% correct.

But running ddr4 at 2400 Mhz, makes me a bit nervous. especially with this many in a 64 bits config (and that 4 times) . and it has to run at max speed for this project.
(It is kind of funny thinking about it..running transceivers @ 25 Gbps don't scare me at all)

this protoype will cost a lot of pennies, so i would prefer not waisting a pretty expensive FPGA and PCB.

yes there will be a compensation inside of the chips / tooling to get optimum preformance but still all documentation says you have to take internal wirebonds into account. so here I am doing that and there is no real guide of how to do it. it is going to be simulated, but does the simulation (post layout) take the timing of the internal wirebonds? or is it just pin to pin.? I am having a meeting about this today so hope to have a answer soon...

now i get the option in the schematic symbol to add the lengths of internal wirebond to the pins, and that is great. but the fun doesn't stop there.. how to match this..
I have broken down the 16 bits config to 2x8 to ease routing, so I can match the 16 bits on 2 layers making it possible. doing 16 bits and dqs / dm on one layer isn't even possible.
grouping signals in a control/ byte groups. and then i should match this over 64 bits.. thats sounds like impossible right?

I am at pre layout stage here, just figuring out on what layers to use... and still have a lot to do (see screenshot)

so any advice or experience is welcome.

in the end I will figure it out.. I always do, but having some help along the way is always nice!

anyway... Thanks for helping so far!


Best regards,
Paul..

[robertferanec]

that lead me to contact xilinx themselves, and the answer was that you should not trust the matching on the defkits, since they are not likely to be 100% correct.

- I love this kind of feedback. Some of my clients have same experience with other manufacturers too

you have to take internal wirebonds into account.

- I would expect this internal wirebonds to be able to be compensated also in the delay registers, but that is only my thinking. Why I am thinking this? After you compile the FPGA design, I would be very surprised if all the signals are "delay matched" ... so it doesn't really matter if delay is due FPGA implementation or if it is in wirebonds.

But as I said, that is only what I would expect .. I have never tried that and I may be wrong.

I am curious what you will find out, please let me know.

[Paul van Avesaath]

Hi Robert,

I understand your reasoning, but when running the DDR4 @ 2400 MHz (or 1200 clk) the margins are within the 5 ps. this means (in my opninion) that getting the PCB layout as close to perfect will help a lot giving you a larger margin for the FPGA to work with. anyway, I am working through this one interface first and having it simulated. I will have awnsers soon I hope they will be positive!.

now to get the Xsignals working ont his design and start routing..

keep you posted!

[Paul van Avesaath]

update number one!

after introducing Xsignals to the settings, things became much more clear. I do not have to group the signals like i did in the excel file. altium does this for you, so just calculating the the picoseconds to mill is good enough and putting them into the schematic symbol. which kind of makes sense, because otherwise changing the pin file in vivado would mess up all calaculations.

we are learning every day!

xsignals it self is pretty handy but still a lot of headaches.

keep you posted!

[robertferanec]

If you are using xSignals, maybe this will help you: https://www.fedevel.com/welldoneblog...useful-things/

[Paul van Avesaath]

Whatching it over and over again

[Paul van Avesaath]

Hi Robert,

since you are the expert in Xsignals. I have the following issue. I have swapped a few bits in one byte cluster, but by doing this my xsignals have gone crazy.. it looks like xsignals does not recognize the new definition. but I cant find how to fix it.

now it says Broken and when you look at the primitives attached you can see the swap I made (manually by moving the netnames in the schematic) but it does not update the link..

I am hesitant to re run the xsignals since I already have routed the flyby of the controller. and do not want to screw things up.

any suggestions?

[Paul van Avesaath]

well figured it out again, just manually re add the xsignals will fix the broken link.. I dont know if pinswapping is allowed within xsignals, but that still a manual thing for me..
but hey it works... i am a Happy panda again!

[robertferanec]

yes, if you swap pins, you may really need to adjust the xSignal definitions.

[Paul van Avesaath]

Hi Guys,

ok added the new " updated" signals and got it to work.. no more broken links.
it is going for simulation this week..

just one question.. I red that the red signals in the xsignal panel, just mean that they are the longest signals. not that there is anywthing wrong with the,, e.g. a maximum length rule that is telling me that they are too long right?

[robertferanec]

Honestly, I do not know what the red means But I know they all should be white when everything is ok