Announcement

Collapse
No announcement yet.

Design Rule checker

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • Design Rule checker

    Hi,

    This is the first time I have used the Fedevel forum and I am already a customer of the Academy Video Course.

    I am trying to modify an existing PCB Design using Altium, by making the board smaller and improving the fanout before going through EMC testing and certification. After I rotate the imx6 processor and the memory by 90 degrees, and moving the fucials and some of the capactiors/resistors, and it then says it is failing the Design Rules even though they have not changed. The Design rules are <3mm proximity and <10mm for vertical.

    Existing Design:

    (See attached image)(Design already routed)

    As you can see there is no ‘Green’ components to indicate a Design Rule violation, but, when I re-organise below:

    (See attached image)

    The Capacitors/resistors in the bottom right are causing a violation with the 200pin connector whilst the fudicals are causing a violation in close proximity the memory and to the iMX6 chip. This was not causing a problem before and it is now and I do not know why, or, how to correct it/ignore it.

    Is anyone able to advise?

    Many Thanks

    Sam M

  • #2
    Hello millensg, please do you know what exactly these errors are? Could you run DRC (go to your PCB, then: Tools -> Design Rule Check -> Run Design Rule Check ...) and click on the PCB button (in the bottom right corner) -> PCB Rules and Violations. This could help you. If you are still not sure, please attach screenshot of the PCB Rules and Violations window.

    Comment


    • #3
      I did what you suggested and it brought up quite a few errors, and also managed to filter by component clearance. This got myself thinking so I went back to the previous Design even though it was not showing any 'Green' to indicate Design rule violations and just run the Design Rule Check, it showed plenty. The Design was orignally produced on PowerPCB and Powerlogic, quite old even for a newbie. I managed to get the designs exported into ASCII by a Design Company that already had PADS so I could then import into Altium. I guess this really showed Altium to be a lot more powerful and useful as a tool.

      Back to the connector, If I highlight it, it shows its close proximity to a number of components even though it is just a row of SMT pads that slot into the 200 pin connector that it mounts into. Therefore, it probably does not need to be that size and I wonder if i could alter it in the component library to take up less space that it really does on the board (When the board is inserted into the connector).

      Comment


      • #4
        If the problem is component collision, you have more options:

        1) Check what is the current component clearance rule (go to your PCB and: Design -> Rules -> Placement -> Component Clearance -> ComponentClearance )

        2) Update your component footprint. Generate PCB library (go to your PCB and: Design -> Make PCB Library), edit the footprint and import it back to your PCB (go to your "PCB library" panel, right click on the footprint you would like to update in your PCB and use "Update PCB with ...")

        3) If you are sure what you are doing, you can set a rule to ignore component collision. Have a look here: http://www.fedevel.com/designhelp/fo...ing-violations

        I hope it helps

        Comment


        • #5
          My apologies not getting back straght away as I found a few niggles:

          1) Importing PADS ASCII files do not put all the same information in the same .PrjPCB file i.e Schematics, layout and library files. This you need to do yourself after import.

          2) Some of the windows are too large for the screen and therefore cannot access it. Need to find an ideal screen resolution, or, I am trailling WINDOWSPACE that allows me to move the open window around using CTRL+WIN+ARROW KEYS.

          If you look at my last post the connector is highlited. it treats the whole connector as the boundary for the <3MM clearance (White box is the component boundary) and not the instances within the component, as photo attached. I wonder if I would need to modify the component to remove the holes and add them seperately to the layout, or, is their another way to get Altium to skirt around the holes so as not to treat the whole image as one block and its boundary?

          Comment


          • #6
            200 PIN connector.

            Comment


            • #7
              Normally, we include mounting holes as separate components. They are part of schematic, placed into PCB and locked down. But, it depends on engineer - everybody doest it differently.

              Comment


              • #8
                Thanks for that, it means I can place components closer to the connector. The remaining issue I have is the fudicals causing a placement violation between the fudicals themselves and the memory chips, as the fudical (components) are placed on the corners. When I check the violations on the fudicals on the IMX6 BGA it only shows the violations for the BGA itself.

                How does Altium know when to ignore clearance violation on a Fudical component?

                Many Thanks

                (Image Attached).

                Comment


                • #9
                  In this particular case you have to make exceptions for the fiducials in the rules, the way Robert demonstrates in the link provided above. Are you sure you need those additional fiducials for the BGAs anyway? Most of the time, if the assembler is decent you will be fine just with 3 fiducials in the corners of the board.

                  Comment


                  • #10
                    I agree with mairomaster. We also used to put couple of fiducials close to the big chips, but in recent designs we only place them into PCB corners or on the panel - no problems. But of course, you may want to check with your assembly house.

                    Here is a screenshot of a rule how to ignore clearance violation:

                    Click image for larger version

Name:	fetch?id=408&amp;d=1444651412&amp;type=full.jpeg
Views:	33
Size:	180.7 KB
ID:	705

                    Comment

                    Working...
                    X