| FORUM

FEDEVEL
Platform forum

DRAM_ADRS_CNTRL Group length match

meet , 12-05-2017, 11:57 PM
Hello Robert,

In lesson-4, while reffering the net length match for ADRS-CNTRL group, i found a correction in spread sheet. please refer the snap shot for more details.

Query,

In spread sheet " IMX-6 Rex Module DDR3 Length Calculator-Spread sheet.xls" length for signal "DRAM_SDCLE0" is not entered for layer 2 which is 17Mil. Could you please tell why it is mentioned 0.
During your vedio i found it as 17 and no negative values. (Pic-4)
Could you please the reference document shared for lesson 4
robertferanec , 12-06-2017, 11:49 AM
From just looking at these pictures it looks like there should be 17. I am not sure why there is 0 - maybe a mistake? A very good spot @meet
meet , 12-06-2017, 09:12 PM
Thank you Robert,
one more concern is, if i enter the length as 17 mil to correct it, than final difference with clock signal comes as negative(-). Total length becomes more than clock length. Is it fine for design or clock length should not be exceeded.
Could you please brief?
robertferanec , 12-07-2017, 11:21 AM
I compared the spreadsheet from pic 4 with spreadsheet in pic 3 and the DRAM_SDCKE0 values in the purple and brown column are different. The best is to open the layout which you are checking and measure all the segments of DRAM_SDCKE0 signal. Double check if the lengths are the same as inserted in the spreadsheet. That should help.
meet , 12-07-2017, 11:11 PM
Hello Robert,
Thank you for reply. i have one more query.

1. As shown in attached picture (MEM to VTT) and highlighted RED, i didnt get this signal on PCB. could you please tell which signal is this and where on Schematic.
robertferanec , 12-08-2017, 08:44 AM
These are the last segments for clock tracks - the segments between last memory and termination resistors.
Use our interactive Discord forum to reply or ask new questions.
Discord invite
Discord forum link (after invitation)

Didn't find what you were looking for?