Hi,
I have two questions about DDRx VREF:
1.
Why do the DDRx VREF route with traces and not a plane or polygon? I see this method in IMX6 project and some other projects. Is there any consideration or limitation for using plane area for DDRx VREF?
2.
Where to place VREF resistor voltage divider (as VREF source) when we have 4 or more DDRx that connected to FPGA and so they are in different sides of FPGA? Should place VREF source near power section or ...? Is there any consideration?
Thanks
I have two questions about DDRx VREF:
1.
Why do the DDRx VREF route with traces and not a plane or polygon? I see this method in IMX6 project and some other projects. Is there any consideration or limitation for using plane area for DDRx VREF?
2.
Where to place VREF resistor voltage divider (as VREF source) when we have 4 or more DDRx that connected to FPGA and so they are in different sides of FPGA? Should place VREF source near power section or ...? Is there any consideration?
Thanks
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