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  • DDR4 layout

    I've taken over a half finished layout and is trying to decide if to start over or just adjust obvious mistakes and then do simulation in HyperLynx DDRx and hope for the best (we will probably rent HyperLynx when we have a design worth the effort).

    The board has 12 layers, and two of the signal layers are sandwiched between ground and (DDR4) power layers. It's 0.13mm pre-preg between signal layer and ground and 0.15mm pre-preg between signal layer and power plane.

    The power planes are not continuous, but sliced into ground and power rails at a point where most of the CAC signals is crossing. I suspect it will have impact on SI for the board.

    Any thoughts on this? Has anyone done SI simulation with split power planes near DDR4 CAC signals?

    Last edited by linux-dude; 03-27-2018, 10:23 AM.

  • #2
    I have done some boards where one side is solid GND and the other side has chunks of power planes - works oki, no problems. However, in these cases the reference plane would only be the one GND solid plane. Also, if my board has, memory interface I always use two solid GNDs planes above and below the signal layer(s) or if not possible I use one solid GND plane and one solid power plane (a good power plane such 3V3 or 1.5 / 1.8V memory power plane). I do not use split power planes above memory tracks.

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    • #3
      Originally posted by robertferanec View Post
      I have done some boards where one side is solid GND and the other side has chunks of power planes - works oki, no problems. However, in these cases the reference plane would only be the one GND solid plane. Also, if my board has, memory interface I always use two solid GNDs planes above and below the signal layer(s) or if not possible I use one solid GND plane and one solid power plane (a good power plane such 3V3 or 1.5 / 1.8V memory power plane). I do not use split power planes above memory tracks.
      Thanks for answering Robert!

      I ripped it up and started all over. My plan was to do exactly that, i.e. use solid ground planes on each side of the DDR4 bus. However, i noticed that the DDR4 data sheet (MT40A256M16GE-083E:B) explicitly states that CAC should be referenced to VDD, so i'm not entirely sure how this should be set up - with a 12 layer board, partly coupling to ground is inevitable (i.e. stack-up similar to GND / DDR4-CAC / VDD) no matter how i do.

      Any suggestions?

      Thanks!

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      • #4
        I would check how reference design implements this, but if I would not be sure I would probably use GND on one side and VDD on the other side. But I need to say, some design guides even do not speak about this - so I am not 100% when it starts to be important.

        This is what I found here https://www.micron.com/~/media/docum...ign_guide.pdf:

        Typical routing for DDR4 components requires two internal signal layers, two surface signal layers, and four other layers ( 2 VDD and 2 VSS) as solid reference planes.

        DDR4 memories have VDD and VDDQ pins, which are both typically tied to the PCB VDD plane. Likewise, component VSS and VSSQ pins are tied to the PCB VSS plane. Each plane provides a low-impedance path to the memory devices to deliver VSSQ. Sharing a single plane for both power and ground does not provide strong signal referencing. With careful design, it is possible for a split-plane design to work adequately:

        • Designs should reference data bus signals to VSS.
        • CA bus and clock should reference VDD.
        • Signals should never reference VPP.

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        • #5
          Originally posted by linux-dude View Post
          I've taken over a half finished layout and is trying to decide if to start over or just adjust obvious mistakes and then do simulation in HyperLynx DDRx and hope for the best (we will probably rent HyperLynx when we have a design worth the effort).

          The board has 12 layers, and two of the signal layers are sandwiched between ground and (DDR4) power layers. It's 0.13mm pre-preg between signal layer and ground and 0.15mm pre-preg between signal layer and power plane.

          The power planes are not continuous, but sliced into ground and power rails at a point where most of the CAC signals is crossing. I suspect it will have impact on SI for the board.

          Any thoughts on this? Has anyone done SI simulation with split power planes near DDR4 CAC signals?

          have made the the DDR4 design with split planes, als long as you keep the planes continous beneath the signals then it is ok. so you have to move the planes if possible.
          like robert mentioned you will need at least one solid plane for GND for the project.

          ik must say that whoever writes those papers, lives in the perfect world.. real life it is compromise compromise and compromise in your design.
          good luck!

          also simulate the hell out of it

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