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What Should be The Impedance of DATA & Single Ended Signals of DDR Memory Layout ?

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  • What Should be The Impedance of DATA & Single Ended Signals of DDR Memory Layout ?

    Dear All,
    Dear Robert,

    This is regarding iMAX6Q processor based hardware design which is similar to Open Rex development board.

    In DDR memory layout I am using 100 Ohms impedance control for differential pair signals and what should be the impedance for the other signals like Data and ODT single ended signals ? Is that okay to use 50 Ohms or 80 Ohms ?

    1) Differential Pair like following - 100 Ohms
    DRAM_CLK0_P
    DRAM_CLK0_N ...etc

    2) Data Signals like following; What should be the impedance ?
    DRAM_D1
    DRAM_SDODT0 ....etc

    I must be thankful to you if you can give me an idea on this as soon as possible.

    Regards,
    Kulunu.

  • #2
    Kulunu, I apologize for late replay. I was travelling (I was speaking at CDNLive conference).

    NX/Freescale has a good design guide. The guide covers this topic:
    https://www.nxp.com/docs/en/user-gui...6DQ6SDLHDG.pdf

    On the page 42 (just under memory rules) you can find the following note:
    "Finally, the impedance for the signals should be 50 OHM for single ended and 100 OHM for differential pairs."

    Comment


    • Kulunu
      Kulunu commented
      Editing a comment
      Dear Robert,

      Many thanks for your response.

      I have another question. I'm refering to OpenRex hardware design layout of yours. There you have 12 layers and how did your PCB manufacturers control single ended signals of DDR Memory Layout in Layer 2 and Layer 11 up to 50 Ohms ? I mean what are the reference layers did they take for impedance control ?
      I'm having an issue with the PCB manufacturer as they cann't meet 50 Ohms with single ended signals in memory layout of my custom hardware. I using your reference design of OpenRex as a reference for stack-up and memory layout.

      Could you please help me on this ? Could you please shear how did your manufacturer control impedance and what are their reference layers ?

      Regards,
      Kulunu.

  • #3
    OpenRex is using 10 Layer PCB. L2 and L9 are GND planes with short tracks. We do not do controlled impedance of these short tracks (we do not have controlled impedance on L2 and L9)

    Comment


    • Kulunu
      Kulunu commented
      Editing a comment
      Hi Robert,

      Thank you.

      But on L2 layer and L11 layer have DDR DATA single ended routing. Those single ended tracks should control impedance up to 50 Ohms according to NXP. (Page 42 >> https://www.nxp.com/docs/en/user-gui...6DQ6SDLHDG.pdf )

      Don't we need to control single ended DDR signal and DATA signals in different layers.

      Regards & Thnaks,
      Kulunu.

  • #4
    I am sorry I forgot, OpenRex is using through hole design. There are no short tracks on layers 2 and 9.

    Are you referring to the iMX6 Rex module? Because on iMX6 Rex module, there is 12 layer PCB and L2 + L11 are grounds with short tracks. You are right, there is no controlled impedance on L2 and L11. Because impedance can not be controlled on L2 and L11, the tracks are only very short. We had to use the L2 and L11 for these tracks, because we needed to keep uVIAs small.

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