reference plane

[Guest]

here I atatched 3 layers (layer3 power, layer 4 signal, layer 5 GND).
As it can be seen, in layer 3, we have not uniform plane. Due to the interrupted plane in layer 3, we should consider this layer as a reference for signal layer 4 (symmetric Stripline) or not (Embedded Microstri) ?

[robertferanec]

In some cases, I may consider the power plane as reference plane (e.g. if memory power plane is above or below memory signals). If the power plane is completely broken, I do not consider it as reference plane.

Also, what I normally do, I place the solid GND plane much closer to the signal layer (e.g. 75um or 3 mil) and I place the power plane much further, so even if you try to consider the power plane to be reference plane, the effect will not be huge (you can play with impedance calculator, place one reference plane close to signal layer, try to place another reference plane far away from the signal layer, watch the results as you play with distance of the further reference plane).

[Guest]

thank you robert,
what should we do in 4 layers board, (for example signal layer, gnd plane, pwr plane and signal layer) in this case we only have to route in top layer layer the controlled impedance traces and in the bottom layer not controlled signals?

[robertferanec]

yes, ideally you would like to route impedance controlled tracks only on the layer above GND

[Petar]

Hello, I have another question: what if (in this case L3) the power plane is not related to the IC (where the differential pairs are connected to) and also it can't be placed much further than L5. Does L3 needs to be considered and how?

[robertferanec]

If on L3 will be broken planes not related to signal on L4 and L5 would be GND placed much further than L3 ..... I would not design stackup this way. Calculation of impedance for signals on L3 can be inaccurate and also, it is questionable how the return currents would flow. I would re-think how to reorder the stackup.