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Understanding length matching specifications in DDR/QDR memories

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  • Understanding length matching specifications in DDR/QDR memories

    Hello to all, this is my first post.

    Becoming from RF world I recently migrated to PCB routing in high speed digital designs, so I take care about signal integrity, crosstalk, impedance matchng, etc, I must route all signals between QDR memory (CY7C2665KV18) and very fast FPGA from microsemi. Regarding "QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide" App Note AN4065 from Cypress at page 11 says:

    All Data, Address and Clock lines must be matched
    closely within ±10 ps within each bus type and
    between buses. Alternatively, in terms of length, the
    matching translates to +/-60 mils using 160 ps per
    inch of trace length. Also Clock lines should be kept
    away from other signal and Clock lines to a minimum
    of 5x the trace width or larger if space allows.

    Ok, the tolerances are specified in picoseconds I tried to determine how much is in terms of length, so first able, let's take 160ps per inch as speed of electromagnetic wave in the medium (PCB dielectrics):

    160 ps -> 1 inch -> 25.4 mm
    +/-10ps -> +/-0.0625 inch -> +/-1.5875 mm

    If I calculate the speed of EM Wave in the medium (I use er= 3.6 and it's close to reality), v = c/sqrt(3.6) = 158.138e6 m/s, so for 10 picoseconds this lead us around 1.58 mm, very close to first calculation. However 2 experienced routers in high speed digital design says me (with no technical arguments, just empirical) that this is a very broad tolerance, they use normally around +/-0.2 mm. Taking these remarks as true, I could be wrong in a factor x10,

    1.- What's could be wrong in my reasoning ?
    2.- What are the orders of tolerance most used for routing DDR 2,3 etc?
    3.- Is in my particular case a huge tolerance (1.58mm) or Im completely wrong? This is important because of relationship with routing difficulty.

    PS: I not find anything about package length matching, this reinforces my hypothesis that the tolerances advised by my colleagues are too tight, recall that 0.2mm is 1.26ps using 160ps per inch, and no differential buses appart clock signals, but they're running only at 550MHz maximum clock frequency.

    Thanks in advance

  • #2
    You estimations should be alright, considering the coincide with design guide information. People often use much tighter length matching just because it doesn't hurt - many times it's not necessary though. Also as you mentioned, sometimes it might be benefitial if the inside package length matching is quite bad, approaching the limits.

    I've routed DDR3 with +/-1mm without problems. Normally it's a good idea to stick to the manufacturer guidance.


    • #3
      Thabk you very much that was I'm looking for. One real reference of magnitude from anyone who had routed succesfully DDR3.


      • #4
        I agree. I have been thinking many times about tolerances in design guides which are very often too tight (e.g. length match within 5 mil - theoretically, you can do it, practically, is the length really going to be length matched within 5mil?).

        However, as mairomaster mentioned, when you re doing length matching, it takes almost the same time to length match signals within 60mils as length matching them within 10 mil. So, I often do length matching very tight (high speed parallel signals usually within 10 mils, differential pairs within pair within 5 mils).

        If chip manufacturer says nothing about length in package, I assume, they did length matching inside the chip.

        PS: your numbers are ok. Here is an example of DDR3 design guide: On page 40, you can see they recommend to length match ADDR signals within 50 mils (+/- 25), your +/-60mil is not much further from it


        • #5
          Ok Thank you very much to both. This is my first "extreme" routing so I'd like to take care, because I have no "feeling" of previous experience.