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Need Help Understanding Board Stack-up and Layer Impedance

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  • Need Help Understanding Board Stack-up and Layer Impedance

    I'm fairly new at high speed layout, and am designing a 100MHz board based on the Cyclone IV E Altera FPGA.
    I started with the DE2-115 Terasic/Altera evaluation board, and am trying to create a custom board for it.

    This board's highest speed devices are listed here, and all but the ethernet is operating at 100MHz:

    2 ea IS42S16320F-6TLI (DRAM Memory)
    1 ea S29GL064N90TFI010 (FLASH Memory)
    1 ea 88E1111-B2-RCJ1C000 (Ethernet Phy)
    2 ea AD9254BCPZ-150 (100MHz ADC)

    My question is, can you please tell me how to do a board stack-up?
    How do I chose the right stackup, and target impedance for the board, to allow me to impedance match the signals?
    What should be my considerations for this, and where do I start.


  • #2
    This may help you with stackup: https://www.fedevel.com/welldoneblog/?s=stackup

    For impedance, ideally you would like to follow design guides. If you can not find any useful documentation, try to google for "com express design guide". For example, check page 182 here: https://www.picmg.org/wp-content/upl...013-12-061.pdf

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    • #3
      Thank you Robert!

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