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SDR SDRAM layout recommendations

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  • #16
    Looking at the ibis files for the IO pins of the mcu and the flash chip they both set the model_type to I/O, so I would change that line for the ram chip aswell, could be a mistake from the manufacturer. Yes, when the chip select is disabled, all data lines are set to HiZ.

    Without modifying the ibis file I managed to simulate the ram chip as in input with altium setting the ram chip pin as Tri/In with input model: I_O_tp_tri.mac and output model: I_O_tp_out.mac. Is this what you did?

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    • #17
      We didn't use Altium. I really wanted and I really tried, but I have really bad experience with Altium simulations - it keeps crashing all the time and I don't fully trust the results. I tried different experiments and some results are weird - of course I have to say I am not expert for simulations in Altium, so I may be doing something wrong.

      For example now, I just wanted to try it again ... and I am not able to add model into the library - as soon as I click on "Add Signal Integrity" Altium keeps crashing and crashing and crashing .... even after I switched off and switched on the software

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      • #18
        I didn't do my simulations with altium either, but gave it a try to see if I could do the simulation which you were having problems.

        Yes exactly! I had the same results. If I imported an ibis model from the signal integrity window, for the mcu case it would start crashing getting millions of crash popups, very annoying. I had to add it directly to the schematic symbol. For the ram ibis i had to manually edit it because altium was complaining about something weird.

        In any case, you may be able to use the component library I sent you and then export a test board to a better simulator like hyperlynx or similar, this is what I do.

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        • #19
          I will try Thank you faluco

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          • #20
            Robert, do you have any experience or information about doing a timing budget analysis for the sdram signals?

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            • #21
              faluco is not hyperlynx ddr simulation offering that? To simulate ddr I normally recommend to use Hyperlynx DDRx wizard - passing that simulation is usually enough to feel confident about the layout.

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              • #22
                I don't have access to Hyperlynx, I did the previous signal integrity simulations with a different software :\

                Basically the budget consists on taking the setup and hold times of mcu and ram and with the help of a spreadsheet or similar you calculate the min and max lengths of the tracks in relation to the clock. This is important to see if the clock track needs to be lengthened with respect to other tracks to agree with the timing constraints.

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                • #23
                  I do not have any SDRAM length matching requirements, but I would say there is probably something on the Internet e.g. Hardware Tips for Point-to-Point System Design: Termination, Layout, and Routing. Have a look around, I am sure you will find something helpful.
                  Attached Files

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                  • #24
                    Thanks Robert! I will take a look. There's no so much about it, many of the references are about DDR, it seems the SDR technology is a bit obsolete

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