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  • faluco
    replied
    Thanks Robert! I will take a look. There's no so much about it, many of the references are about DDR, it seems the SDR technology is a bit obsolete

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  • robertferanec
    replied
    I do not have any SDRAM length matching requirements, but I would say there is probably something on the Internet e.g. Hardware Tips for Point-to-Point System Design: Termination, Layout, and Routing. Have a look around, I am sure you will find something helpful.
    Attached Files

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  • faluco
    replied
    I don't have access to Hyperlynx, I did the previous signal integrity simulations with a different software :\

    Basically the budget consists on taking the setup and hold times of mcu and ram and with the help of a spreadsheet or similar you calculate the min and max lengths of the tracks in relation to the clock. This is important to see if the clock track needs to be lengthened with respect to other tracks to agree with the timing constraints.

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  • robertferanec
    replied
    faluco is not hyperlynx ddr simulation offering that? To simulate ddr I normally recommend to use Hyperlynx DDRx wizard - passing that simulation is usually enough to feel confident about the layout.

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  • faluco
    replied
    Robert, do you have any experience or information about doing a timing budget analysis for the sdram signals?

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  • robertferanec
    replied
    I will try Thank you faluco

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  • faluco
    replied
    I didn't do my simulations with altium either, but gave it a try to see if I could do the simulation which you were having problems.

    Yes exactly! I had the same results. If I imported an ibis model from the signal integrity window, for the mcu case it would start crashing getting millions of crash popups, very annoying. I had to add it directly to the schematic symbol. For the ram ibis i had to manually edit it because altium was complaining about something weird.

    In any case, you may be able to use the component library I sent you and then export a test board to a better simulator like hyperlynx or similar, this is what I do.

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  • robertferanec
    replied
    We didn't use Altium. I really wanted and I really tried, but I have really bad experience with Altium simulations - it keeps crashing all the time and I don't fully trust the results. I tried different experiments and some results are weird - of course I have to say I am not expert for simulations in Altium, so I may be doing something wrong.

    For example now, I just wanted to try it again ... and I am not able to add model into the library - as soon as I click on "Add Signal Integrity" Altium keeps crashing and crashing and crashing .... even after I switched off and switched on the software

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  • faluco
    replied
    Looking at the ibis files for the IO pins of the mcu and the flash chip they both set the model_type to I/O, so I would change that line for the ram chip aswell, could be a mistake from the manufacturer. Yes, when the chip select is disabled, all data lines are set to HiZ.

    Without modifying the ibis file I managed to simulate the ram chip as in input with altium setting the ram chip pin as Tri/In with input model: I_O_tp_tri.mac and output model: I_O_tp_out.mac. Is this what you did?

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  • robertferanec
    replied
    Originally posted by faluco View Post

    32800D:
    [Model] I/O
    Model_type 3-state

    vs

    16800F:
    [Model] I/O
    Model_type I/O

    Maybe altium does not like the 3-state line in Model_type, you could try editing that line and set it to I/O and see if you can make it work as an input too.
    Yes, that is exactly the thing. I was able to set it up as a 3 state pin, but I could not simulate it as an input. The big question is: "Is there a reason why they did the model this way or it's just inaccurate?". For example, if the chip is not enabled, does it mean, that all the data lines are in HiZ? Because that could influence the simulation. Also, when the 32800D is reading, how do I then set it up as an input?

    Thank you very much for the components

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  • faluco
    replied
    Sure Robert! The forum doesn't allow me to upload the library, so I've sent it to your email.

    This is my setup, so you can do it the same way as me: I simulated the DATA0 signal, the ram chip is the output and the flash and mcu are set as inputs.
    The DATA0 signal is assigned to the following pins:
    1) MCU: pin PD14 (no.116)
    2) flash: pin no.35
    3) ram: pin no.2

    In theory when you import the IBIS file, you should pick the model that is assigned to the pin you want to simulate, for the MCU pin no.116 I used io8p11_arsudq_ft, io_mv for the flash pin and I/O for the ram chip. Each IBIS file contains a collection of models, you will see that each one starts with the [Model] syntax.
    Basically, for 3-state pins, there's also an enable signal that you have to enable to make the model work as an output, otherwise it will be Z and it'll be set as an input. For example, in the MCU ibis file you can find this for an IO model:

    Model_type I/O
    Polarity Non-Inverting
    Enable Active-Low

    That enable signal is set to active low, so when you set it to 0 the model will behave as an output, otherwise as an input. Unfortunately I haven't done my simulations with Altium, but i can try to set it up and see if I can make it work.
    Comparing the ibis files of both ram chips (IS42S16800F vs IS42S32800D) i see this big difference:

    32800D:
    [Model] I/O
    Model_type 3-state
    Polarity Non-Inverting
    Enable Active-High

    vs

    16800F:
    [Model] I/O
    Model_type I/O
    Polarity Non-Inverting
    Enable Active-High

    Maybe altium does not like the 3-state line in Model_type, you could try editing that line and set it to I/O and see if you can make it work as an input too.

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  • robertferanec
    replied
    Fantastic! Your pictures are pretty similar to ours. It's a very interesting example of showing up, that it really matters how you route the tracks. Each branch length in our simulation was 30mm long. What I am not sure about is, if or how to include the length in the package when you will be doing the layout.

    faluco please, would it be possible to send me Schematic Symbol & PCB Footprint of the three components? I would like to try to simulate it also in Altium and I would need the full component to be able to assign the IBIS model to it. BTW, for simulation I didnt use the exact model of IS42S32800D-7TL, I used the one with smaller memory size (IS42S16800F) because IS42S32800D IBIS didn't give me option to set data pin as input (I am not really sure what was the reason do not include input pin in the IBIS model). What model did you use or how did you set the "Technology" type in Altium?

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  • faluco
    replied
    Thanks for the time taken to do this!

    The star topology simulation has very interesting results! What was the track length of the star's branches?

    These are the results I'm getting, using the the same layout you posted above and with the 47R resistor:

    1) fly-by topology (black:MCU, red:flash, green:ram):
    Click image for larger version

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ID:	1232) star topology (same colors) (The branches of the simulated star measure 20mm):
    Click image for larger version

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    Looking how bad things get with long tracks, I have no idea how older motherboards worked with this kind of memory

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  • robertferanec
    replied
    I played with Altium Simulator, but I am not 100% sure about it's results, so I decided to change simulator. I had to ask friend of mine to simulate it for you. Here are some results - no guarantee

    It looks like, the best way to route the data signals is to use STAR (all the branches same) + 47R Series termination resistors (you may want to play with the best value) placed close to the SDRAM. You will need to set the CPU pins to be the strongest. VERY Important: You need to keep the tracks short - for long tracks, the results are getting really bad.

    Here are some screenshots. I hope it helps. What were your results, are there similar to ours?



    The worst case
    Placing series termination resistor close to the CPU (U1, input, blue color), setting up MEMORY as Output (U2, green), routing all parts in one line (I did not actually placed the chips in one line, as there will be some tracks inside the package, so I made a small stub)
    ​ Click image for larger version

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    Click image for larger version

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    The optimum case
    Placing series termination resistor close to the SDRAM, setting up MEMORY as Output (green color), routing all the branches same length
    Click image for larger version

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    Click image for larger version

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  • faluco
    replied
    Oh!

    It's +3V3.

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