Internal Signal layer referenced to Power plane broken

[Naveen-Krishnan]

Thanks Robert Feranec for your reply. I will cross check with the PCB house.

[robertferanec]

12µm outer layer copper thickness

12um may be just material thickness, you may need to add another 20um of copper for plating, so total thickness would be 32um. Double check with your PCB manufacturer.

[Paul van Avesaath]

18 micro is plenty, as long as you keep the plane as wide as you can...

[Naveen-Krishnan]

Hello,

I have another question.

My PCB fabricator can design boards with 12µm outer layer copper thickness and 18µm inner layer copper thickness.

The impedance requirements are met but I am doubtful regarding the power supplying capacity.

My power supply has 3A supply(VDDIODDR & VDDCORE), so 12µm outer and 18µm inner copper thickness is sufficient for so much of power. Please help me out.

Please find attached the screenshot of the stackup.

[Naveen-Krishnan]

Thanks Robert Feranec. I have spreaded the signal, I believe this is to avoid cross talk ?

Please can you tell me whether the space between tracks is enough , please.

[robertferanec]

From what you are trying to achieve it looks ok to me. You do not really have many options in this stackup. The hardest thing is probably to fanout the CPU by using through hole VIAs. Then I see you try to switch to Layer 3 (L1), that is what I would do too. Just do not forget to spread the signals so there is big space between the tracks.

[Naveen-Krishnan]

Hello,

I have opted for Advanced PCB and Schematic course and tried to follow all the routing guidelines. I have doubt and fear that the ETHERNET would work or not. I routed RMII interface for Ethernet above VCC Power plane. The VCC power plane has broken planes like VCCHSIC, VCCCORE etc. As it is a high speed interface, I have a doubt that it would work or not. Please help me.

Please find attached the screenshots of the stackup
1. TOP
2. GND
3. L1
4. L2
5. VCC
6. BOTTOM

In the VCC plane the empty places i will be pouring VCC3.3Volts and Inner layer 1 will be pouring GND so that I get Stripline traces in the inner layers. Please help me, I cannot find a solution.

Regards,
Naveen