Naming ports and signals

[Paul van Avesaath]

Dear Robert and mr.Paul I appreciate your comments!! I'm junior in engineering and also new in working at a company with many people. I'm part of the RnD department as SCH/PCB designer. But my main concern nowadays is how someone manage the "communication" between his colleagues. By "communication" I mean schematics, naming convention, folder structure (for back up purposes and continuation of the project if an engineer leaves the company) and stuff like that.
Again I thank you for your comments. I've got an idea of what I have to do from now on.
Best regards, Kostas.

good luck then! and if you have found a good way please report back.. always good to see how things end up.. maybe you will give me something to think about!

about the structure.. that all depends on what system is in place.. I manually back up stuff to a read only file system just to have full control and dont have the hassle of a SVN orsomthing.. never learned how to work with that... and for me it is great!

[robertferanec]

how someone manage the "communication" between his colleagues. By "communication" I mean schematics, naming convention, folder structure (for back up purposes and continuation of the project if an engineer leaves the company) and stuff like that.

- Most companies I know have some conventions on some level (e.g. you have to use specific directory structure for project documentation), but they also provide some freedom (you can name nets in your schematics as you like).

[k.ifantidis]

Dear Robert and mr.Paul I appreciate your comments!! I'm junior in engineering and also new in working at a company with many people. I'm part of the RnD department as SCH/PCB designer. But my main concern nowadays is how someone manage the "communication" between his colleagues. By "communication" I mean schematics, naming convention, folder structure (for back up purposes and continuation of the project if an engineer leaves the company) and stuff like that.
Again I thank you for your comments. I've got an idea of what I have to do from now on.
Best regards, Kostas.

[robertferanec]

k.ifantidis most schematics what we use are created based on reference schematics designed by big companies - so you can see what they use.

There may be differences in naming not only between companies but also between boards - e.g. if you are designing FPGA board where functions of pins are highly configurable, then you may need different convention as if you are designing a board with fixed pin functions.

So, I normally follow convention from reference schematic (it could be confusing if half of schematic is done based on reference schematic and the other half based on different convention). Occasionally I do change original net names (e.g. we may rename the power nets, but usually we are not re-naming other peripherals if they are already used in the reference schematic - that would be too risky and possible space for introducing mistakes and errors into the schematic).

[Paul van Avesaath]

Hi,
My opinion is you can do whatever you want as long as you are consistent in you naming.
I am working in a 50+ company but i have changed the way we do schematics significantly.
I do not know about some rule or standard, i try to do what works for us..

the suggestion you gave MCUperiferal_PINorMCUport_HWperipheral_PINdetails ==> SWCLK_PA14_PROG_CLK" is a good start
for me i use a similar way..

FF_01_RX_DIFF_03_p (connector_channel_direction_Type_number_Different ial indicator)
or
SDI_GSPI_SDIN_1_33V (group ID_signal type_signal identifier_group number_signal Voltage)
or
XCVU13P_A_DDR4_ADDR_0 (source_Group_Type_Identifier)
or
QSFP_Port1_TX_2_p (Group_Channel_Type_Number_Differential indicator)

I do not specify the source pin or the destination, an easy search will do that.


it also depends on how complex the schematics are.. for instance when having multiple FPGA's on board. It is wise to identify the source.
like XCVU13P_A_DDR4_ADDR_0 and ZYNQ_A_DDR3_ADDR_0

the voltage designation is easy to see if you are interfacing at the right voltage and helps to keep leveltranslators easy to identify and FPGA's easy to check of they are on the correct bank.



good luck..

[k.ifantidis]

Dear Robert, thank you for your reply.
I've checked the schematics that you've posted. I think there has to be some conventions out there about naming described by a standard (IEC's/IEEE's/IPC's/ISO's maybe?). You know something like a communication protocol. I know that, what I'm asking **limits** someone to some specific *naming/structure/etc rules* but I think if a company has to grow, there should be some "data storing/ data naming/ or something similar" protocols followed.
My aim is my schematics to be easily understandable among my colleagues even after years. I would like to know if someone here in the community who works or has worked in a company with 50++ employs knows how this company copes with data storing structures/ versioning/ backup/ data sharing formats etc. Do companies follow any rules about stuff like that?
If yes where can I find them? Where should I refer to?
I'm sorry if the post becomes out of "Schematic Design & PCB Layout" topic but I would really value the opinion of a more experienced engineer.

Best regards, Kostas.

[robertferanec]

I only have naming standard for Power nets (e.g. +5V_VCC). I do not really have standard for other signals. Often we need to stay compatible with reference schematics, so we can not change it.

However, it is very useful to organize signal names based on interfaces (I2C1_SDA, UART1_TXD, JTAG_TDO, ...), especially if you know you may need to search for them often e.g. start dram signals with DRAM_ because you may need search for all DRAM signals for example during simulation.

Feel free to have a look at our schematics on http://www.imx6rex.com/
Here are some examples:
http://www.imx6rex.com/wp-content/up...-Schematic.pdf
http://www.imx6rex.com/wp-content/up...Production.pdf

[k.ifantidis]

Hello Fedevel community.
I would like to know if there is any naming standard/protocol/format for signals and ports. I would like to achieve readable schematics. For example, if someone reads a port name or net-name in my schematics instantly to know the two ends of this connection. A format that I've made up is like this:
MCUperiferal_PINorMCUport_HWperipheral_PINdetails ==> SWCLK_PA14_PROG_CLK
Things are simple with small designs and small companies but when someone needs to work in a team of engineers (PCB/AssemblyEng/Programmers etc) those stuff get complicated.

Regards, Kostas.