Power rail noise couple

[noisepic]

Due to size constraint I have to layout 24V power rail over inner 3.3V power rail, they're all inner layer wide trace, i make polygon. I'm afraid of noise/ripple from 24V can effect to 3.3V, am I correct? I'm not sure? Might happen?

In system have both high and low voltage any recommendation for layout?

3.3V will supply for SOC, so noise on these voltage is the killer for the board.

[Paul van Avesaath]

yes they can effect each other. if you have the posseblitiy to put a ground plane in between it will help.. but it all depends on how much noise there is on the 24 volts.. also if you use sufficient caps over a wider range eg, 47uF, 22uF, 10 uF, 2u2, 100nF 10nf, it can really reduce the noise from a power supply. there are also plenty of filters to create with few components to really bring down noise.. with regards to you 3.3V, what is the source? an LDO? a switch mode? (usually a SOC can handle a lot of abuse before the voltage supply is a problem. but you have to measue it on the prototype to see if things are as you expected..

[robertferanec]

We often create power input plane (6-24V) over some other planes (e.g. 3.3V, 5V) and no problems. Here are a few things what you may want to consider.
- ideally route the 24V as small as possible and only in the area where it is needed, Maybe route it on TOP / BOTTOM layer
​- as suggested by Paul van Avesaath, use GND plane(s) to separate 24V plane from the rest of the circuit
- consider your stackup and do not place 24V on the layer which is close (e.g. 0.075mm) to another layer with important signals. Place the 24V on the layer which is further from the other layers.

If 24V is going to be very noisy, it should be routed away from other signals and you should take a special care to filter it (if it's very noisy, that would not only be problem on your board, but it would cause also problems during EMC and EMI tests).