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Best way DDR3 Bus routing

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    robertferanec
    Administrator

  • robertferanec
    replied
    Normally you have ratio for standard through hole VIAs like 1:10 (or 1:12), for uVIAs it is for example 1:1. This for example means, usually the smallest hole for standard 1.6mm PCB is 0.15mm and for 100um laser hole in uVIA it means you only can drill 100um deep. You can drill also smaller VIAs e.g. you can use 6mil drill bit, but this is going to cost you a lot of money as you only can drill like 100 holes with that drill.
    Some time ago I made a video in PCB factory, if you like, have a look: https://youtu.be/f6_svRNJYls?t=232

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  • Paul van Avesaath
    Senior Member

  • Paul van Avesaath
    replied
    Originally posted by robertferanec View Post
    - via ratio (minimum size of the hole in VIA depends on how deep you are drilling .... deeper you are drilling bigger hole you need to use = drilling from L1 to L3 would require bigger VIAs and I needed to save some space)
    as long as you are "drilling" wouldn't hole size be the minimum of 8mil? which is big enought to go through the whole board? with laser drilling you can go smaller indeed.. I havent checked that IMX6rex design.. but i dont believe i have ever seen machine drilled holes smaller than 8mil.

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  • robertferanec
    Administrator

  • robertferanec
    replied
    I would to place 4Gb of memory chips
    - there are 4Gb chips which you can use also with current layout.

    Why you don't route directly from L1 to L3?
    - via ratio (minimum size of the hole in VIA depends on how deep you are drilling .... deeper you are drilling bigger hole you need to use = drilling from L1 to L3 would require bigger VIAs and I needed to save some space)

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  • Massimo
    Junior Member

  • Massimo
    replied
    Yes this is a good idea! But my question is born bacause I would to place 4Gb of memory chips and in this case I need to route 3 more signals (CS1, SDCKE1, SDODT1) and it could be a bit difficult to layout the ADDR/CMD/CTRL signals. However, with a little patience I'll do it

    I have noted on the iMX6Rex Project that some data_bank are routed through layer2 (GND) with microvias, and after go to layer3 (Sig). Why you dont't route directly from L1 to L3? Many Thanks

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  • robertferanec
    Administrator

  • robertferanec
    replied
    This can help - here you will see the order how the iMX6Rex module was routed: https://www.youtube.com/watch?v=FtWm8Mm6ZPY
    If you start with data lines, and if you are using similar placement as on iMX6Rex, be sure you have enough space for all the ADDR/CMD/CTRL signals between the memories.

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  • Massimo
    Junior Member

  • Massimo
    replied
    I placed 4 memory chips, 2 on the top and 2 on bottom layer.... the placing is very similar to the imx6Rex project

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  • Paul van Avesaath
    Senior Member

  • Paul van Avesaath
    replied
    yes. how are you placing the DDR3 chips top bottom or one next to the other,
    first picture is ddr3 fly by, second is ddr2 tbranch on top only, third = tbranch clamshell (somehow the text inserted with the foto's did no work properly)
    Paul van Avesaath
    Senior Member
    Last edited by Paul van Avesaath; 11-30-2018, 06:33 AM.

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  • Massimo
    Junior Member

  • Massimo
    replied
    For "clamshell" Do you mean DDR3 T-topology?

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  • Paul van Avesaath
    Senior Member

  • Paul van Avesaath
    replied
    I always start with the addr & ctrl lines... how are you routing them? flyby or clamshell?

    Leave a comment:

  • Massimo
    Junior Member

  • Massimo
    started a topic Best way DDR3 Bus routing

    Best way DDR3 Bus routing

    Hi Everyone,

    I try to routing the DDR3 Bus in T-Branch mode.
    I would like your opinion, is the best way to starting the routing from ADDR & CTRL Lines?

    What do you think??

    Thanks!
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