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Fanout at Course2_Lesson7

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  • Fanout at Course2_Lesson7

    Hello Robert.
    I list below some questions before starting the fanout at Lesson_7 in a "wrong" way. Definately, I'm missing some part of the picture, so please give your perspective on this.

    I’m working on the “easy” DDR example that you include and at the end I have 2 example questions with picture to help me understand the way of thinking.
    1. What fanout pattern I have to follow at the processor chip? Do I have to split it in 4 quarters like the patterns are created by Altium automatic fanout? If I fanout in a wrong way now then I will have to delete everything!
    2. How I can predict at which layer below the chip I have route each group of the chip pins? I start from the center of the chip going to edge but which micro-via I have to use? For which layer?
    3. For the drill pairs (stupid question), why we go with micro-via at the 2nd layer and then we rout them i.e. on the 3rd , instead of creating via pairs that stich from 1st to 3rd layer directly? Is it because of impedances or it is connected with the manufacturing process?
    4. Inside the project of DDR example the Layers 4, 5, 6, 7 are not mentioned in drill pairs. See picture0. Are the acessed only with Trough Via and why without micro-Vias?
    5. The micro-vias are used only for signal layers or there are cases that can be used for power planes as well?
    6. Is it enough to have one layer for GND (L4) and one for Vcc (L7) for this design, from power distribution point of view, or more would be better?
    7. Are the schematics of this DDR card available in order to check the connection pairs?
    8. In picture1, why we place the micro-via in green circle below that pin of the chip? This is connected only with the pin in blue circle. Is it a way to help during the length matching later?
    9. In picture2, in the green frame I should probably fanout the vias pointing up, not down as done in the blue frame (to have more “escape” options). But if I do so, the pin in yellow circle at the top will not be able to follow it? Is it ok to choose another direction (at the right side for example), or I have to do it totally differently?
    Thanks in advance.

  • #2
    1) I do not us automatic fanout. Try to fan out the first two rows out of the BGA, rest of the VIAs I usually place the way it is good for routing. This is explained more in Advanced PCB Layout course.
    2) Again, in Advanced PCB Layout. But, some time ago I wrote an article for altium, this can help:
    3) This can help to answer your question:
    4) They are accessible in through hole VIAs and buried VIAs. This can give you some ideas how different stackups are done: (uVIAs on additional layers = much more expensive PCB)
    5) I do not use uVIAs to transfer power.
    6) Usually number of power planes is defined by CPU (for very complex CPUs you may need 4 power planes). From EMC/EMI point of view ideally you would like to have GND planes on both sides around signal layer
    7) In advanced PCB layout you will be working with our open source project and you can download full documentation here For Advanced Hardware Design Course, the schematic and full layout is not available (for that course we had to use a third party design and they only allowed us to share some information, not the whole project)
    8) No other option to route it, no space.
    9) Yep, layout is sometimes difficult Sometimes you just need to try ... and you will see.


    • #3
      All topics clear . Thanks Robert!