Length matching - top / bottom factor

[antman]

Hi,

I am currently designing a DDR4 layout, and as Robert suggests, JEDEC DDR4 boards are very useful as example. I have downloaded some of these boards (mainly from Micron manufacturer), and I have found something interesting in the excels used for the calculation of length matching. During these calculations, the result, the compensated length, is calculated as the sum of the different transmission lines, but applying a factor of 1.1 to external layers. That is:

TL0 (top) = 3.82mm
TL1 (middle) = 12.23mm
TL2 (top) = 0.57mm

Compensated length = TL0/1.1 + TL1 + TL2/1.1 = 16.21mm

What this factor means and how it is calculated?

Thanks!

pd: I tried to upload the excel but I can't, neither xlsx and csv format.

[robertferanec]

That could be to compensate different signal speed on TOP/Bottom Layers vs inner layers.

PS: I was speaking about different speed in some of my server videos, maybe here: https://www.youtube.com/watch?v=rdlE...Y&t=0s&index=7

[antman]

Hi Robert,

thanks for your post, this is the answer I was thinking about! In the next link, there is some explanation about microstrip and stripline propagation speeds, and if you divide both of them, the result is sqrt(Er)/sqrt(Ereff) ~ 1.1

https://www.protoexpress.com/blog/signal-speed-propagation-delay-pcb-transmission-line/

[robertferanec]

antman thanks for the link