10 results in 0.0076 seconds.
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Thank you very much chitransh92. I'm going to try the keep out solution to see how this work-out. I hope it doesn't keep out the polygon pours. -
I'm posting this [circuitnet discussion about pcb coatings] here because it's interesting. I have been wondering myself if soldermask is an electrical...Leave a comment:
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Yes this is correct but some of the manufacturers does not apply full-tending and I have to be careful in order not to corrupt a brand name or model with...Leave a comment:
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Design rule - Via stiching
Hello there !!
I'm trying for at least 1-2 years now to figure out how to add a rule that will prevent via stitching to be placed on top-overlay/... -
Dear Robert and mr.Paul I appreciate your comments!! I'm junior in engineering and also new in working at a company with many people. I'm part of the...Leave a comment:
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Dear Robert, thank you for your reply.
I've checked the schematics that you've posted. I think there has to be some conventions out there about...Leave a comment:
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Naming ports and signals
Hello Fedevel community.
I would like to know if there is any naming standard/protocol/format for signals and ports. I would like to achieve readable... -
Also a good solution is found here in this link: https://www.eevblog.com/forum/altium/fiducials/
I've just read your post and I wanted to add this...Leave a comment:
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Hello there!
I've just upgraded to AD18 today. As you mention Robert, they moved some buttons, shortcuts seems to be the same, UI changed to black...Leave a comment:
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Hello,
I have found this document when i was searching the same thing on the net. I haven't yet concluded which designing style to use. So if you...Leave a comment:
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